SLVUC68 September   2021 TPSM5601R5H

 

  1.   Trademarks
  2. 1EVM Setup
  3. 2EVM Connectors and Test Points
  4. 3EVM Parameters
    1. 3.1 Maximum Output Current
    2. 3.2 Maximum VIN and VOUT Configurations
    3. 3.3 Switching Node Behavior
  5. 4Typical Performance
    1. 4.1 Typical Characteristics (VIN = 12 V)
    2. 4.2 Typical Characteristics (VIN = 24 V)
    3. 4.3 Typical Characteristics (VIN = 36 V)
    4. 4.4 Typical Characteristics (VIN = 48 V)
  6. 5Feature Description
    1. 5.1 Enable Pin (EN)
    2. 5.2 Power-Good Pin (PGOOD)
    3. 5.3 System Loop Stability
  7. 6Layout
    1. 6.1 PCB Layout
  8. 7Schematic
  9. 8Bill of Materials (BOM)
  10.   Device Support
    1.     Related Documentation
    2. 9.1 Support Resources

2 EVM Connectors and Test Points

Wire-loop test points and scope probe sockets are included for digital voltmeters (DVM) or oscilloscope probes to aid in the evaluation of the device. Table 2-1 describes each test point.

Table 2-1 Test Point Descriptions
TEST POINT(1) DESCRIPTION
VIN S+ Input voltage monitor. Connect the positive lead of a DVM to this point to measure efficiency.
VIN S– Input ground monitor. Connect the negative lead of a DVM to this point to measure efficiency.
–VOUT Sense Negative output voltage monitor. Connect the negative lead of a DVM to this point for measuring efficiency, line regulation, and load regulation.
GND Sense Output ground monitor. Connect the positive lead of a DVM to this point for measuring efficiency, line regulation, and load regulation.
GND System ground test points
VIN Scope (J2) Input voltage scope monitor. Connect an oscilloscope probe to this set of points to measure input ripple voltage.
–VOUT Scope (J3) Negative output voltage scope monitor. Connect an oscilloscope probe to this set of points to measure negative output voltage ripple and transient response.
SYS_EN (J6) System enable select jumper. Use the control header (J6) to enable or disable the device using a jumper. The SYS_EN test point is connected to the level-shifting circuitry to activate the enable circuit. A minimum supply voltage of 5 V on the SYS_EN test point is required to turn on the enable circuitry. Do not exceed 20 V on this test point. Failing to adhere to these constraints can result in damaged components. To monitor the enable signal, monitor the EN_TP testpoint.
VIN_EN (J7) Enable tied to the VIN jumper. The enable pin is tied directly to VIN, which allows the device to start up when VIN is within its valid operating range. The enable test point (EN_TP) is connected directly to the enable pin of the device to monitor the enable signal. Do not connect this test point to ground or any other signal. If enable/disable feature is desired, then use the system enable select jumper (J6).
PGOOD Power-good test point. Monitors the power-good signal of the device. A level-shifting circuitry is implemented on the EVM to allow a proper reading state of the pin.
PG_PU PGOOD pullup test point. Apply 5 V to this pin or any other DC voltage less than 18 V to use as a pullup voltage for the PGOOD signal. A pullup resistor and level-shifting circuitry is implemented on the EVM for proper utilization.
INJ Frequency response test point. Inject a sinusoidal signal to this test point (system) to measure the gain and phase response characterstocs of the device.
(1) Refer to the product data sheet for absolute maximum ratings associated with the features in this table.