The TO_SAFE_SEVERE and TO_SAFE are distinct sequences that occur before transitioning to the SAFE state. Both sequences shut down all rails without delay. The TO_SAFE_SEVERE sequence immediately ceases BUCK switching and enables the pulldown resistors of the BUCKs and LDOs. This is to prevent any damage of the PMICs in case of over voltage on VCCA or thermal shutdown. The timing is illustrated in Figure 6-2. The TO_SAFE sequence does not reset the BUCK regulators until after the regulators are turned off.

After the power sequence shown in Figure 6-2, the TO_SAFE sequence delays the TPS65941213 by 16 ms and the LP876411B4 by 3 ms. The delay ensures that the primary PMIC finishes after the secondary. After these delays, the following instructions are executed on both PMICs:

//TPS65941213 and LP876411B4
// Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xE3
// Reset all BUCK regulators
REG_WRITE_MASK_IMM ADDR=0x87 DATA=0x1F MASK=0xE0

The TO_SAFE_SEVERE sequence executes the following instruction after the power sequence:

// TPS65941213
// Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xE3
// LP876411B4
// Clear CLKMON_EN, set LPM_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xF3

The TPS65941213 has an additional delay of 500 ms at the end of the TO_SAFE_SEVERE sequence. It is important to note that the recovery is not attempted until after the sequence delay is complete.