SLVUCF3 User guide

SLVUCF3 March 2022 DRA829V , LP8764-Q1 , TDA4VM , TPS6594-Q1

6.2 PFSM Triggers

As shown in Figure 6-1, there are various triggers that can enable a state transition between configured states. Table 6-1 describes each trigger and its associated state transition from highest priority (Immediate Shutdown) to lowest priority (I2C_3). Active triggers of higher priority block triggers of lower priority and the associated sequence.

Table 6-1 State Transition Triggers

Trigger	Priority (ID)	Immediate (IMM)	REENTERANT	PFSM Current State	PFSM Destination State	Power Sequence or Function Executed
Immediate Shutdown⁽⁷⁾	0	True	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	SAFE⁽¹⁾	TO_SAFE_SEVERE
MCU Power Error	1	True	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	SAFE⁽¹⁾	TO_SAFE
Orderly Shutdown⁽⁷⁾	2	True	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	SAFE⁽¹⁾	TO_SAFE_ORDERLY
OFF Request	4⁽⁹⁾	False	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	STANDBY⁽²⁾	TO_STANDBY
WDOG Error	5	False	True	ACTIVE	ACTIVE	ACTIVE_TO_WARM
ESM MCU Error	6	False	True	ACTIVE	ACTIVE	ACTIVE_TO_WARM
ESM SOC Error	7	False	True	ACTIVE	ACTIVE	ESM_SOC_ERROR
I2C_1 bit is high⁽³⁾	11	False	True	ACTIVE, MCU ONLY	No State Change	Execute RUNTIME BIST
I2C_2 bit is high⁽³⁾	12	False	True	ACTIVE, MCU ONLY	No State Change	Enable I²C CRC on I²C1 and I²C2 on all devices.⁽⁴⁾
ON Request	15	False	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	ACTIVE	TO_ACTIVE
WKUP1 goes high	16	False	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	ACTIVE
NSLEEP1 and NSLEEP2 are high⁽⁵⁾	17	False	False	STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM	ACTIVE
NSLEEP1 goes low and NSLEEP2 goes low⁽⁵⁾	21	False	False	ACTIVE, MCU ONLY	Suspend-to-RAM	TO_RETENTION
NSLEEP1 goes high and NSLEEP2 goes low⁽⁵⁾	22	False	False	ACTIVE, MCU ONLY	Suspend-to-RAM	TO_RETENTION
I2C_0 bit goes high⁽³⁾	23⁽⁸⁾	False	False	STANDBY, ACTIVE, MCU ONLY	LP_STANDBY⁽²⁾	TO_STANDBY
I2C_3 bit goes high⁽³⁾	24⁽⁸⁾	False	False	ACTIVE, MCU ONLY	No State Change	Devices are prepared for OTA NVM update.⁽⁶⁾

(1) From the SAFE state, the PFSM automatically transitions to the hardware FSM state of SAFE_RECOVERY. From the SAFE_RECOVERY state, the recovery counter is incremented and compared to the recovery count threshold (see RECOV_CNT_REG_2, in Table 5-10). If the recovery count threshold is reached, then the PMICs halt recovery attempts and require a power cycle. Refer to the datasheet for more details.

(2) If the LP_STANDBY_SEL bit is set in the TPS65941213-Q1 (see RTC_CTRL_2, in Table 5-10), then the PFSM transitions to the hardware FSM state of LP_STANDBY. When LP_STANDBY is entered, then please use the appropriate mechanism to wakeup the device as determined by the means of entering LP_STANDBY. Refer to the datasheet for more details. LP_STANDBY_SEL in the LP876411B4-Q1 is not applicable to the PFSM triggers.

(3) I2C_0, I2C_1, I2C_2 and I2C_3 are self-clearing triggers.

(4) Enabling the I²C CRC, enables the CRC on both I2C1 and I2C2, however, the I2C2 is disabled for 2ms after the CRC is enabled. Be aware when using the watchdog Q&A before enabling I²C CRC. The recommendation is to enable the I²C CRC first, and then after 2ms, start the watchdog Q&A.

(5) NSLEEP1 and NSLEEP2 of the primary PMIC can be accessed through the GPIO pin or through a register bit. If either the register bit or the GPIO pin is pulled high, the NSLEEPx value is read as a high logic level.

(6) After completion of an OTA update, the processor is required to initiate a reset of the PMICs to apply the new NVM settings.

(7) These triggers can originate from either the TPS65941213 or the LP876411B4.

(8) Trigger IDs 23 and 24 are not available until the NSLEEP bits are masked: NSLEEP2_MASK=NSLEEP1_MASK=1.

(9) Trigger IDs 3, 25, and 26 (not shown) are enabled and activated by the power sequences. These triggers are used to manage the transition between the PFSM and the FSM.