SLVUCF3 March   2022 DRA829V , LP8764-Q1 , TDA4VM , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 TO_ACTIVE
      6. 6.3.6 TO_RETENTION
  8. 7Application Examples
    1. 7.1 Initialization
    2. 7.2 Moving Between States; ACTIVE and RETENTION
      1. 7.2.1 ACTIVE
      2. 7.2.2 RETENTION
    3. 7.3 Entering and Exiting Standby
    4. 7.4 Entering and Existing LP_STANDBY
    5. 7.5 Runtime Customization
  9. 8References

5.3 BUCK Settings

These settings detail the voltages, configurations, and monitoring of the BUCK rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in Section 6.3.

After the Section 6.3.5 sequence has completed, the BUCKx_EN bit is set for BUCK1, BUCK4, and BUCK5 in the TPS65941213. BUCKx_EN is set for the BUCK1 in the LP876411B4. The BUCKx_VMON_EN bit is set for BUCK1, BUCK3, BUCK4 and BUCK5 in the TPS65941213. The BUCKx_VMON_EN bit is set for BUCK1 in the LP876411B4. The BUCKx_RV_SEL bit is cleared for all BUCKs. The other bits remain unchanged, but are still accessible via I2C.

Table 5-3 BUCK NVM Settings
Register NameField NameTPS65941213-Q1LP876411B4-Q1
ValueDescriptionValueDescription
BUCK1_CTRLBUCK1_EN0x0Disabled; BUCK1 regulator0x0Disabled; BUCK1 regulator
BUCK1_FPWM0x0PFM and PWM operation (AUTO mode).0x0PFM and PWM operation (AUTO mode).
BUCK1_FPWM_MP0x0Automatic phase adding and shedding.0x0Automatic phase adding and shedding.
BUCK1_VMON_EN0x0Disabled; OV, UV, SC and ILIM comparators.0x0Disabled; OV, UV, SC and ILIM comparators.
BUCK1_VSEL0x0BUCK1_VOUT_10x0BUCK1_VOUT_1
BUCK1_PLDN0x1Enabled; Pull-down resistor0x1Enabled; Pull-down resistor
BUCK1_RV_SEL0x1Enabled0x1Enabled
BUCK1_CONFBUCK1_SLEW_RATE0x35.0 mV/μs0x35.0 mV/μs
BUCK1_ILIM0x55.5 A0x55.5 A
BUCK2_CTRLBUCK2_EN0x0Disabled; BUCK2 regulator0x0Disabled; BUCK2 regulator
BUCK2_FPWM0x0PFM and PWM operation (AUTO mode).0x0PFM and PWM operation (AUTO mode).
BUCK2_VMON_EN0x0Disabled; OV, UV, SC and ILIM comparators.0x0Disabled; OV, UV, SC and ILIM comparators.
BUCK2_VSEL0x0BUCK2_VOUT_10x0BUCK2_VOUT_1
BUCK2_PLDN0x1Enabled; Pull-down resistor0x1Enabled; Pull-down resistor
BUCK2_RV_SEL0x1Enabled0x1Enabled
BUCK2_CONFBUCK2_SLEW_RATE0x35.0 mV/μs0x35.0 mV/μs
BUCK2_ILIM0x55.5 A0x55.5 A
BUCK3_CTRLBUCK3_EN0x0Disabled; BUCK3 regulator0x0Disabled; BUCK3 regulator
BUCK3_FPWM0x0PFM and PWM operation (AUTO mode).0x0PFM and PWM operation (AUTO mode).
BUCK3_FPWM_MP0x0Automatic phase adding and shedding.0x0Automatic phase adding and shedding.
BUCK3_VMON_EN0x0Disabled; OV, UV, SC and ILIM comparators.0x0Disabled; OV, UV, SC and ILIM comparators.
BUCK3_VSEL0x0BUCK3_VOUT_10x0BUCK3_VOUT_1
BUCK3_PLDN0x1Enabled; Pull-down resistor0x1Enabled; Pull-down resistor
BUCK3_RV_SEL0x0Disabled0x0Disabled
BUCK3_CONFBUCK3_SLEW_RATE0x51.3 mV/μs0x210 mV/μs
BUCK3_ILIM0x55.5 A0x44.5 A
BUCK4_CTRLBUCK4_EN0x0Disabled; BUCK4 regulator0x0Disabled; BUCK4 regulator
BUCK4_FPWM0x0PFM and PWM operation (AUTO mode).0x0PFM and PWM operation (AUTO mode).
BUCK4_VMON_EN0x0Disabled; OV, UV, SC and ILIM comparators.0x0Disabled; OV, UV, SC and ILIM comparators.
BUCK4_VSEL0x0BUCK4_VOUT_10x0BUCK4_VOUT_1
BUCK4_PLDN0x1Enabled; Pull-down resistor0x1Enabled; Pull-down resistor
BUCK4_RV_SEL0x1Enabled0x0Disabled
BUCK4_CONFBUCK4_SLEW_RATE0x35.0 mV/μs0x210 mV/μs
BUCK4_ILIM0x55.5 A0x44.5 A
BUCK5_CTRLBUCK5_EN0x0Disabled; BUCK5 regulator
BUCK5_FPWM0x0PFM and PWM operation (AUTO mode).
BUCK5_VMON_EN0x0Disabled; OV, UV, SC and ILIM comparators.
BUCK5_VSEL0x0BUCK5_VOUT_1
BUCK5_PLDN0x1Enable Pull-down resistor
BUCK5_RV_SEL0x1Enabled
BUCK5_CONFBUCK5_SLEW_RATE0x35.0 mV/μs
BUCK5_ILIM0x33.5 A
BUCK1_VOUT_1BUCK1_VSET10x370.800 V0x370.800 V
BUCK1_VOUT_2BUCK1_VSET20x370.800 V0x370.800 V
BUCK2_VOUT_1BUCK2_VSET10x370.800 V0x370.800 V
BUCK2_VOUT_2BUCK2_VSET20x370.800 V0x370.800 V
BUCK3_VOUT_1BUCK3_VSET10xfd3.30 V0x00.3 V
BUCK3_VOUT_2BUCK3_VSET20xfd3.30 V0x00.3 V
BUCK4_VOUT_1BUCK4_VSET10x410.850 V0x00.3 V
BUCK4_VOUT_2BUCK4_VSET20x410.850 V0x00.3 V
BUCK5_VOUT_1BUCK5_VSET10xb21.80 V
BUCK5_VOUT_2BUCK5_VSET20xb21.80 V
BUCK1_PG_WINDOWBUCK1_OV_THR0x3+5% / +50 mV0x3+5% / +50 mV
BUCK1_UV_THR0x3-5% / -50 mV0x3-5% / -50 mV
BUCK2_PG_WINDOWBUCK2_OV_THR0x3+5% / +50 mV0x3+5% / +50 mV
BUCK2_UV_THR0x3-5% / -50 mV0x3-5% / -50 mV
BUCK3_PG_WINDOWBUCK3_OV_THR0x7+10% / +100mV0x0+3% / +30mV
BUCK3_UV_THR0x7-10% / -100mV0x0-3% / -30mV
BUCK4_PG_WINDOWBUCK4_OV_THR0x3+5% / +50 mV0x0+3% / +30mV
BUCK4_UV_THR0x3-5% / -50 mV0x0-3% / -30mV
BUCK5_PG_WINDOWBUCK5_OV_THR0x3+5% / +50 mV
BUCK5_UV_THR0x3-5% / -50 mV