SNAU264 July   2021 CDCDB800

 

  1. 1 Trademarks
  2. 2 General Description
    1. 2.1 Features
  3. 3 Quick Setup
    1. 3.1 Setup Procedure
  4. 4 Signal Path and Control Switches
  5. 5 Power Supplies
  6. 6 Clock Inputs
    1. 6.1 Configuring Board for CDCDB803
  7. 7 Clock Outputs
  8. 8 Using SMBus
    1. 8.1 CDCDB803 SMBus Address
  9. 9 Schematics
  10. 10Bill of Materials

4 Signal Path and Control Switches

The CDCDB800 supports single-ended or differential clocks on CLKin_P (J1) and CLKin_N (J2). To achieve the maximum operating frequency and lowest additive jitter, TI recommends to use a differential input clock with high slew rate (>3 V/ns).

The device provides up to 8 LP-HCSL outputs with pin-selectable output enable (HCSL, or Hi-Z).

All control pins are configured with the control DIP switch, S1. Table 3-1 shows this default setting, and Table 4-1 shows the REFout enable logic.

Table 4-1 REF out Enable Selection
REFout Enable ModeS1[1:7] REFout_EN State
Disabled/Hi-ZOFF
EnabledON