SNLA293 Application note

7.1 TDR Testing Procedure

Table 7-1 TDR Run Procedure

Sequence	Description	Register Read/Write
Step 1: For DP83TC811 as master	Force the link-down by writing register and enable link-partner to go silent. Wait for ~1s after register write. In case of valid open and short cable faults, TDR will still work fine without step 1. For good cable case, TDR register 0x001E may show Fail on bypassing this step.	Write register[0x0475] = 0x0008
Step 1: For DP83TC811 as slave	Link-partner should be made silent. In case of valid open and short cable faults, TDR will still work fine without step 1. For good cable case, TDR register 0x001E may show Fail on bypassing this step.	If DP83TC811 is the link partner, then Write register [0x0475] = 0x0008 Else, Check with the PHY vendor about how to make link partner silent
Step 2	Start TDR	0x001E[15] = 1
Step 3	Wait for 100ms (should be sufficient for TDR to converge for maximum cable length)
Step 4	Check wether TDR is completed successfully	Read 0x001E[1:0] = [TDR done : TDR fail]. Value should be [1,0]. Fault type/locations are valid only if this correct value is read. Value other than [1,0] will mean that there is some noise/signal on the line which is causing TDR to fail.
Step 5	Fault type and location is read.	Read register 0x016B for fault status and fault type. 0x016B[9] = 0 indicates that no fault is detected If a valid fault is detected, then register 0x016B[9:8] = 'b11(short) or 'b10(open) In this case, the fault location is read as 1.5 * decimal(0x016B[7:0])