The PHYs have to comply with IEEE 802.3 100BaseTX or 100BaseFX.
The DP83826 is a IEEE 802.3 compliant 100BASE-TX Ethernet PHY, see section 9.1 in the data sheet
The PHYs have to support 100 Mbit/s Full Duplex links.
DP83826 supports full duplex operation for both 10Mbit/s and 100Mbit/s, see section 9.5.1, register BMSR(address 0x1)
The PHYs have to provide an MII (or RMII/RGMII1) interface.
The DP83826 provides a MII and RMII interface connection, see section 9.1 in the data sheet)
Notice that the typical latency of the RMII interface (in general) is higher than the EtherCAT® specified latency requirement.
The PHYs have to use auto-negotiation in 100BaseTX mode.
Has an Auto-negotiation feature which can be enabled or disabled with the strap option, see section 9.3.1 in the data sheet
The PHYs have to support the MII management interface.
Supports the serial management interface up to a maximum clock rate of 24 MHz (MII management interface). This is in section 9.3.9 in the data sheet.
The PHYs have to support MDI/MDI-X auto-crossover in 100BaseTX mode.
Supports MDI/MDI-X auto-crossover reception, see section 9.3.2 in the data sheet
PHY link loss reaction time (link loss to link signal/LED output change) has to be faster than 15 μs to enable redundancy operation.
Fast link-Drop functionality called FLD which shortens the observation window to 10 μs before enabling the link loss indication, see section 8.6 “Fast Link Pulse Timing” and 220.127.116.11 in the data sheet.
The PHYs must not modify the preamble length.
The DP83826 does not modify the preamble length.
The PHYs must not use IEEE802.3az Energy Efficient Ethernet.