SNLA389A December   2021  – May 2022 DP83TC812R-Q1 , DP83TC812S-Q1 , DP83TC813R-Q1 , DP83TC813S-Q1 , DP83TC814R-Q1 , DP83TC814S-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Hardware Configuration
    1. 2.1 Schematic
  4. 3Software Configuration
  5. 4Testing PMA
    1. 4.1 PMA Testing Procedure
  6. 5Testing IOP: Link-up and Link-down
    1. 5.1 IOP Testing Procedure
  7. 6Testing SQI
    1. 6.1 SQI Value Interpretation
  8. 7Testing TDR
    1. 7.1 TDR Testing Procedure
  9. 8Testing EMC and EMI
  10. 9Revision History

PMA Testing Procedure

Note:
  • Before programming any of the test modes, DP83TC81x should be loaded with the respective initialization register configuration (master or slave) as described in Section 3.
  • Test mode 1 requires the link to be established between DUT and link-partner, hence register [0x1] should read as 0x65 before running the test.
Table 4-1 Programming PMA Test Modes
TEST MODEMMDREGISTERVALUE
Test Mode 1x010x08360x2000
Test Mode 2x010x08360x4000
Test Mode 4: Tx_Tclk 25 MHz on the CLKOUT pin.x010x08360x8000

x01

0x045F

0x000D (DP83TC812, DP83TC814)

0x0007 (DP83TC813)

Test Mode 5x010x08360xA000