SNLU278 March 2021 DS160PR412 , DS160PR421

4 SHARE Registers

Table 4-1 lists the SHARE registers. All register offset addresses not listed in Table 4-1 should be considered as reserved locations and the register contents should not be modified.

Table 4-1 SHARE Registers

Offset	Acronym	Register Name	Section
0x0E	SEL_Override	Select Input Override	Go
0x0F	SEL_Val	Select Input Value	Go
0xE2	General	General Control Register	Go
0xF0	DEVICE_ID0	Device ID0 Register	Go
0xF1	DEVICE_ID1	Device ID1 Register	Go

Complex bit access types are encoded to fit into small table cells. Table 4-2 shows the codes that are used for access types in this section.

Table 4-2 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read only access
Write Type
R/W/SC	R/W/SC	Read / Write access, Self-Clearing
Reset or Default Value
-n		Value after reset or the default value

4.1 Select Override Register (Offset = 0x0E) [reset = 0x00]

Select Override is shown in Table 4-3.

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Table 4-3 Select Input Override Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	RESERVED	R	0x0	Reserved
5	RESERVED	R	0x0	Reserved
4	RESERVED	R	0x0	Reserved
3	RESERVED	R	0x0	Reserved
2	SEL_OV	R/W	0x0	Select Input Override 0 = SEL Pin Value, 1 = Override
1	RESERVED	R	0x0	Reserved
0	RESERVED	R	0x0	Reserved

4.2 Select Value Register (Offset = 0x0F) [reset = 0x00]

Select Value is shown in Table 4-4.

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Table 4-4 Select Value Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	RESERVED	R	0x0	Reserved
5	RESERVED	R	0x0	Reserved
4	RESERVED	R	0x0	Reserved
3	RESERVED	R	0x0	Reserved
2	SEL_VAL	R/W	0x0	Select Value 0 = Port A, 1 = Port B
1	RESERVED	R	0x0	Reserved
0	RESERVED	R	0x0	Reserved

4.3 General Register (Offset = 0xE2) [reset = 0x0]

General is shown in Table 4-5.

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Table 4-5 General Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	rst_i2c_regs	R/W/SC	0x0	Device Reset Control: Reset all I2C registers to default values (self-clearing).
5	RESERVED	R	0x0	Reserved
4	RESERVED	R	0x0	Reserved
3	RESERVED	R	0x0	Reserved
2	RESERVED	R	0x0	Reserved
1	RESERVED	R	0x0	Reserved
0	RESERVED	R	0x0	Reserved

4.4 DEVICE_ID0 Register (Offset = 0xF0) [reset = X]

DEVICE_ID0 is shown in Table 4-6.

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Table 4-6 DEVICE_ID0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	RESERVED	R	0x0	Reserved
5	RESERVED	R	0x0	Reserved
4	RESERVED	R	0x0	Reserved
3	device_id0_3	R	X	Device ID0 [3:1]: DS160PR412 = 111 DS160PR421 = 101
2	device_id0_2	R	X	see MSB
1	device_id0_1	R	X	see MSB
0	RESERVED	R	X	Reserved

4.5 DEVICE_ID1 Register (Offset = 0xF1) [reset = 0x27]

DEVICE_ID1 is shown in Table 4-7.

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Table 4-7 DEVICE_ID1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	device_id1_7	R	0x0	Device ID1: 0010 0111
6	device_id1_6	R	0x0	See MSB
5	device_id1_5	R	0x1	See MSB
4	device_id1_4	R	0x0	See MSB
3	device_id1_3	R	0x0	See MSB
2	device_id1_2	R	0x1	See MSB
1	device_id1_1	R	0x1	See MSB
0	device_id1_0	R	0x1	See MSB