SNLU278 March 2021 DS160PR412 , DS160PR421

5 CHANNEL Registers

Table 5-1 lists the CHANNEL registers. All register offset addresses not listed in Table 5-1 should be considered as reserved locations and the register contents should not be modified.

Note that the register offset is provided for the channel 0 or channel 2 registers (channel bank 0 or channel bank 1). For the channel 1 registers on the channel bank 0 (or the channel3 on the channel bank 1), add 0x20 to the provided offset.

Table 5-1 CHANNEL Registers

Offset	Acronym	Register Name	Section
0x0	RX_DET_STS	Receiver Detect Status Register	Go
0x1	EQ_CTRL	Equalizer Control Register	Go
0x2	GAIN_CTRL	DC Gain and VOD Control Register	Go
0x3	RX_DET_CTRL1	Receiver Detect Control Register 1	Go
0x9	RX_DET_CTRL2	Receiver Detect Control Register 2	Go

Complex bit access types are encoded to fit into small table cells. Table 5-2 shows the codes that are used for access types in this section.

Table 5-2 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read only access.
Write Type
R/W	R/W	Read / Write access.
Reset or Default Value
-n		Value after reset or the default value.

5.1 RX_DET_STS Register (Offset = 0x0) [reset = 0x0]

RX_DET_STS is shown in Table 5-3.

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Table 5-3 RX_DET_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
7	rx_det_comp_p	R	0x0	Rx Detect Positive Polarity Status: 0: Not detected 1: Detected The value is latched.
6	rx_det_comp_n	R	0x0	Rx Detect Negative Polarity Status: 0: Not detected 1: Detected The value is latched.
5	RESERVED	R	0x0	Reserved
4	RESERVED	R	0x0	Reserved
3	RESERVED	R	0x0	Reserved
2	RESERVED	R	0x0	Reserved
1	RESERVED	R	0x0	Reserved
0	RESERVED	R	0x0	Reserved

5.2 EQ_CTRL Register (Offset = 0x1) [reset = 0x9]

EQ_CTRL is shown in Table 5-4.

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Table 5-4 EQ_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	eq_en_bypass	R/W	0x0	Enable CTLE Stage 1 Bypass: 0: Bypass disabled 1: Bypass enabled
5	eq_bst1_2	R/W	0x0	CTLE Boost Stage 1 Control.
4	eq_bst1_1	R/W	0x0	See MSB
3	eq_bst1_0	R/W	0x1	See MSB
2	eq_bst2_2	R/W	0x0	CTLE Boost Stage 2 Control.
1	eq_bst2_1	R/W	0x0	See MSB
0	eq_bst2_0	R/W	0x1	See MSB

5.3 GAIN_CTRL Register (Offset = 0x2) [reset = 0x3]

GAIN_CTRL is shown in Table 5-5.

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Table 5-5 GAIN_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	RESERVED	R	0x0	Reserved
5	RESERVED	R	0x0	Reserved
4	RESERVED	R	0x0	Reserved
3	RESERVED	R	0x0	Reserved
2	eq_hi_gain	R/W	0x0	Set CTLE DC Gain: 0: 0 dB (Recommended) 1: 3.5 dB
1	drv_sel_vod_1	R/W	0x1	TX VOD Select: 00: - 6 dB 01: -3.5 dB 10: -1.6 dB 11: 0 dB (Recommended)
0	drv_sel_vod_0	R/W	0x1	See MSB

5.4 RX_DET_CTRL1 Register (Offset = 0x3) [reset = 0x0]

RX_DET_CTRL1 is shown in Table 5-6.

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Table 5-6 RX_DET_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	RESERVED	R	0x0	Reserved
5	RESERVED	R	0x0	Reserved
4	RESERVED	R	0x0	Reserved
3	RESERVED	R	0x0	Reserved
2	mr_rx_det_man	R/W	0x0	Manual override of rx_detect.
1	en_rx_det_count	R/W	0x0	Enable RX detect valid counter.
0	sel_rx_det_count	R/W	0x0	Select valid detect count before enable: 0: 2x consecutive valid detections 1: 3x consecutive valid detections

5.5 RX_DET_CTRL2 Register (Offset = 0x9) [reset = 0x0]

RX_DET_CTRL2 is shown in Table 5-7.

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Table 5-7 RX_DET_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	RESERVED	R	0x0	Reserved
5	RESERVED	R	0x0	Reserved
4	RESERVED	R	0x0	Reserved
3	RESERVED	R	0x0	Reserved
2	mr_rx_det_rst	R/W	0x0	RX Detect Reset
1	RESERVED	R	0x0	Reserved
0	RESERVED	R	0x0	Reserved