SNLU302 March   2025 DS320PR810 , DS320PR822

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Device Configuration Through External EEPROM
  5. 2Register Map Overview
    1. 2.1 Share Registers
    2. 2.2 Channel Registers
  6. 3Equalization Control Settings
  7. 4CTLE Index and Flat Gain Selection Matrix
  8. 5Example Programming Sequences
    1. 5.1 Set CTLE Gain Level
    2. 5.2 Set CTLE Flat Gain Level
    3. 5.3 Set PD Control
    4. 5.4 Set SEL Input (DS320PR822)
  9. 6References

5.3 Set PD Control

The PD functionality of the DS320PR810 can be controlled individually for each channel or broadcast to all channels. This can be particularly useful for applications which require power-down functionality for PCIe link-widths which are smaller than x4 (such as x2 or x1). Table 5-4 shows an example sequence to power down or power on all channels.

Table 5-4 Sequence to Broadcast Power Down or On to All Channels
Step Register Set Operation Register Address
[HEX]		 Register Value
[HEX]		 Write Mask
[HEX]		 Comment
1 Bank 0: Channels 0-3 Write 0x85 0x80 0xFF Power down all channels 0-3
0x7F 0xFF Power on all channels 0-3
2 Bank 1: Channels 4-7 Write 0x85 0x80 0xFF Power down all channels 4-7
0x7F 0xFF Power on all channels 4-7

Assuming 0x18 and 0x19 are the SMBus addresses for Channel Banks 0 and 1, respectively, the following is the XML batch script of the sequence in Table 5-4:

<i2c_write addr="0x18" count="0" radix"16">85 80</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">85 80</i2c_write>
<i2c_write addr="0x18" count="0" radix"16">85 7F</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">85 7F</i2c_write>