SNLU302 March   2025 DS320PR810 , DS320PR822

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Device Configuration Through External EEPROM
  5. 2Register Map Overview
    1. 2.1 Share Registers
    2. 2.2 Channel Registers
  6. 3Equalization Control Settings
  7. 4CTLE Index and Flat Gain Selection Matrix
  8. 5Example Programming Sequences
    1. 5.1 Set CTLE Gain Level
    2. 5.2 Set CTLE Flat Gain Level
    3. 5.3 Set PD Control
    4. 5.4 Set SEL Input (DS320PR822)
  9. 6References

5.1 Set CTLE Gain Level

The DS320PR810 requires manual CTLE tuning. The CTLE gain level can be changed by modifying the value of each CTLE stage (CTLE Boost Stage 1 and 2) or by bypassing the EQ1 stage. The CTLE level may be set individually for each channel or broadcast to all channels. Table 5-1 shows an example sequence for setting the CTLE gain level to CTLE Index 2, Flat Gain (DC Gain) to 0dB on the Bank 0 channels and to CTLE Index 6, Flat Gain (DC Gain) to 0dB on the Bank 1 channels using individual writes to each channel. Use register values provided in Table 4-1 to set the CTLE gain level to any other available index.

Table 5-1 Sequence to Set CTLE Level on Each Channel Individually
Step Register Set Operation Register Address
[HEX]		 Register Value
[HEX]		 Write Mask
[HEX]		 Comment
1 Bank 0: Channel 0 Write 0x01 0x98 0x7F Set CTLE Stage 1 & 2 1st Order Boost Control to Index 2 on Channel 0.
2 Bank 0: Channel 0 Write 0x03 0x05 0x78 Set CTLE Stage 1 2nd Order Boost Control to Index 2 on Channel 0.
3 Bank 0: Channel 1 Write 0x21 0x98 0x7F Set CTLE Stage 1 & 2 1st Order Boost Control to Index 2 on Channel 1.
4 Bank 0: Channel 1 Write 0x23 0x05 0x78 Set CTLE Stage 1 2nd Order Boost Control to Index 2 on Channel 1.
5 Bank 0: Channel 2 Write 0x41 0x98 0x7F Set CTLE Stage 1 & 2 1st Order Boost Control to Index 2 on Channel 2.
6 Bank 0: Channel 2 Write 0x43 0x05 0x78 Set CTLE Stage 1 2nd Order Boost Control to Index 2 on Channel 2.
7 Bank 0: Channel 3 Write 0x61 0x98 0x7F Set CTLE Stage 1 & 2 1st Order Boost Control to Index 2 on Channel 3.
8 Bank 0: Channel 3 Write 0x63 0x05 0x78 Set CTLE Stage 1 2nd Order Boost Control to Index 2 on Channel 3.
9 Bank 1: Channel 4 Write 0x01 0x08 0x7F Set CTLE Stage 1 & 2 1st Order Boost Control to Index 6 on Channel 4.
10 Bank 1: Channel 4 Write 0x03 0x0D 0x78 Set CTLE Stage 1 2nd Order Boost Control to Index 6 on Channel 4.
11 Bank 1: Channel 5 Write 0x21 0x08 0x7F Set CTLE Stage 1 & 2 1st Order Boost Control to Index 6 on Channel 5.
12 Bank 1: Channel 5 Write 0x23 0x0D 0x78 Set CTLE Stage 1 2nd Order Boost Control to Index 6 on Channel 5.
13 Bank 1: Channel 6 Write 0x41 0x08 0x7F Set CTLE Stage 1 & 2 1st Order Boost Control to Index 6 on Channel 6.
14 Bank 1: Channel 6 Write 0x43 0x0D 0x78 Set CTLE Stage 1 2nd Order Boost Control to Index 6 on Channel 6.
15 Bank 1: Channel 7 Write 0x61 0x08 0x7F Set CTLE Stage 1 & 2 1st Order Boost Control to Index 6 on Channel 7.
16 Bank 1: Channel 7 Write 0x63 0x0D 0x78 Set CTLE Stage 1 2nd Order Boost Control to Index 6 on Channel 7.

Assuming 0x18 and 0x19 are the SMBus addresses for Channel Banks 0 and 1, respectively, the following is the XML batch script of the sequence in Table 5-1:

<i2c_write addr="0x18" count="0" radix"16">01 98</i2c_write>
<i2c_write addr="0x18" count="0" radix"16">03 05</i2c_write>
<i2c_write addr="0x18" count="0" radix"16">21 98</i2c_write>
<i2c_write addr="0x18" count="0" radix"16">23 05</i2c_write>
<i2c_write addr="0x18" count="0" radix"16">41 98</i2c_write>
<i2c_write addr="0x18" count="0" radix"16">43 05</i2c_write>
<i2c_write addr="0x18" count="0" radix"16">61 98</i2c_write>
<i2c_write addr="0x18" count="0" radix"16">63 05</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">01 08</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">03 0D</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">21 08</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">23 0D</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">41 08</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">43 0D</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">61 08</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">63 0D</i2c_write>

Table 5-2 shows an example sequence to set the CTLE gain level to CTLE Index 2, 0dB Flat Gain (DC Gain) on Bank 0 channels and to CTLE Index 6, 0dB Flat Gain (DC Gain) on Bank 1 channels using a broadcast write to each channel bank.

Table 5-2 Sequence to Broadcast CTLE Level to All Channels
Step Register Set Operation Register Address
[HEX]		 Register Value
[HEX]		 Write Mask
[HEX]		 Comment
1 Bank 0: Channels 0-3 Write 0x81 0x98 0x7F Set EQ to Index 2 on Channels 0-3.
2 Bank 0: Channels 0-3 Write 0x83 0x05 0x78 Set EQ to Index 2 on Channels 0-3.
3 Bank 1: Channels 4-7 Write 0x81 0x08 0x7F Set EQ to Index 6 on Channels 4-7.
4 Bank 1: Channels 4-7 Write 0x83 0x0D 0x78 Set EQ to Index 6 on Channels 4-7.

Assuming 0x18 and 0x19 are the SMBus addresses for Channel Banks 0 and 1, respectively, the following is the XML batch script of the sequence in Table 5-2:

<i2c_write addr="0x18" count="0" radix"16">81 98</i2c_write>
<i2c_write addr="0x18" count="0" radix"16">83 05</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">81 08</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">83 0D</i2c_write>