See the Design References section for an Excel calculator that calculates the resistor values for the required specifications.
In this equation, Vref is the internal bandgap reference voltage for the LDO. TPS7A4501-SP has a nominal reference voltage Vref = 1.21 V and this design is targeting Vreg = 5 V, so the following applies:
To choose values, the following guideline is used: The current in the feedback resistors from output to ground of an LDO must be at least 100 times the leakage current into the ADJ pin to avoid output accuracy issues. For TPS7A4501-SP, the leakage current of the ADJ pin is 3 μA (typ). This yields the following inequality:
With R8 = 3.97 kΩ (standard value), the following equation is true:
With these values for R7 and R8, the following equation is valid:
When Vin = Vin_max, the following is true:
Most of the output current comes through R4, so with R4 = 100 Ω, the voltage at Iret is approximately:
5 V + 100 Ω * 20 mA = 7 V
Vreg is referenced to Iret, so relative to the supply ground, Vreg = 7 V + 5 V = 12 V, in which case the LDO enters dropout. If the LDO enters dropout, the LDO loses its power supply rejection (PSR) properties, and the op amp has a reduced positive supply and so has a reduced ability to drive the base of the transistor to provide additional output current. Furthermore, if Vreg droops, the current through R3 will be reduced and the circuit begins to exhibit non-linear behavior. Also, if R6 is too large, the additional voltage drop across R6 further reduces the available headroom for the transistor.
With these considerations in mind, choose R4 = 50 Ω to avoid problems with headroom. It follows that:R3 = 199 * 50 Ω = 9.95 kΩ ≈ 9.88 kΩ (standard value)