SNOAA73 May 2021 LMP2012QML-SP , LMP7704-SP , TPS7A4501-SP

See the Design References section for an Excel calculator that calculates the resistor values for the required specifications.

- Define the input voltage range for the circuit. For this design V
_{in_min}= 0 V, V_{in_max}= 5 V is chosen. - Define the output current range for the circuit. For this design I
_{out_min}= 4 mA, I_{out_max}= 20 mA is selected. - Calculate R
_{7}and R_{8}to set the output voltage for the TPS7A4501-SP LDO. The equation to set the output voltage for this adjustable LDO follows:In this equation, V

_{ref}is the internal bandgap reference voltage for the LDO. TPS7A4501-SP has a nominal reference voltage V_{ref}= 1.21 V and this design is targeting V_{reg}= 5 V, so the following applies:To choose values, the following guideline is used: The current in the feedback resistors from output to ground of an LDO must be at least 100 times the leakage current into the ADJ pin to avoid output accuracy issues. For TPS7A4501-SP, the leakage current of the ADJ pin is 3 μA (typ). This yields the following inequality:

16.67 kΩ ≥ R_{7}+ R_{8}With R

_{8}= 3.97 kΩ (standard value), the following equation is true:R_{7}= 3.97 kΩ * 3.13 = 12,426 Ω ≈ 12.4 kΩ (standard value)With these values for R

_{7}and R_{8}, the following equation is valid:R_{7}+ R_{8}= 3.97 kΩ + 12.4 kΩ = 16.37 kΩ ≤ 16.67 kΩNote: Since this design has a current budget limitation, it is desirable to size R_{7}and R_{8}to be near the limit to minimize this quiescent current contribution. - Define the minimum and maximum currents through R
_{3}. See Design Note #5 before defining these currents. For this design, I_{3_min}= 20 μA, I_{3_max}= 100 μA, is chosen. - Calculate the values for
R
_{1}and R_{2}to set I_{3_min}and I_{3_max}as defined in Design Step #4. To do this, use the first equation along with the specifications for V_{reg}, V_{in_min}, V_{in_max}, I_{3_min}and I_{3_max}. When V_{in}= V_{in_min}, the following equations occur:R_{2}= 250 kΩ (standard value)When V

_{in}= V_{in_max}, the following is true:R_{1}= 62.5 kΩ ≈ 62 kΩ (standard value) - Calculate R
_{3}/ R_{4}to set the required current gain. To do this, use this equation along with I_{out_min}and I_{3_min}.Note: Only the minimum values of I_{out}and I_{3}are required to calculate R_{3}/ R_{4}because it is assumed that Design Note #5 has been followed. - Choose values for R
_{3}and R_{4}. Sizing R_{3}is much less important than sizing R_{4}because headroom issues can arise if care is not taken when sizing R_{3}. To see why, analyze the nodal voltages under the maximum loading condition, I_{out}= I_{out_max}= 20 mA. The load voltage is the following:V_{load}= I_{out_max}* R_{load}= 20 mA × 250 Ω = 5 VMost of the output current comes through R

_{4}, so with R_{4}= 100 Ω, the voltage at I_{ret}is approximately:5 V + 100 Ω * 20 mA = 7 V

V

_{reg}is referenced to I_{ret}, so relative to the supply ground, V_{reg}= 7 V + 5 V = 12 V, in which case the LDO enters dropout. If the LDO enters dropout, the LDO loses its power supply rejection (PSR) properties, and the op amp has a reduced positive supply and so has a reduced ability to drive the base of the transistor to provide additional output current. Furthermore, if V_{reg}droops, the current through R_{3}will be reduced and the circuit begins to exhibit non-linear behavior. Also, if R_{6}is too large, the additional voltage drop across R_{6}further reduces the available headroom for the transistor.With these considerations in mind, choose R

R_{4}= 50 Ω to avoid problems with headroom. It follows that:_{3}= 199 * 50 Ω = 9.95 kΩ ≈ 9.88 kΩ (standard value)