Using the “VPULSE” pulse waveform generator feeding into the TLV3604, the voltage below the 1-Ω load resistance is monitored as OUT_BAR. When the gate of the GaN FET is sufficiently driven, the voltage evident at the drain is approximately 0 V. The following image shows the initial simulation results.
As depicted by Initial Simulation Results, the pulse width is approximately 0.6 ns wider than the design requirement at 3.92 ns. This is partly due to the series resistances on the gate of the EPC2019 that are used to avoid voltage overstress due to inductive ringing. To improve the turn-off time of the GaN FET Driver and GaN FET, the OUTL output of the LMG1020 is shorted to the gate of the EPC2019 as recommended in the Typical Applications section of the LMG1020 5-V, 7-A, 5-A Low-Side GaN and MOSFET Driver For 1-ns Pulse Width Applications data sheet.
Next, the circuit is simulated again to see if the pulse width has been reduced to meet the design requirements.
As illustrated by the simulation results in Simulation Results after Removing Resistor, the width of OUT_BAR is slightly out of the design requirement with a pulse width of 3.37 ns. To further improve the pulse width, a narrower LVDS pulse is sent to the TLV3601. To do this, the pulse width of the generator driving the non-inverting input of the TLV3604, VPULSE is reduced. The generator pulse width is adjusted to 2.5 ns to ensure the pulse width is within the design requirement. Design Compliant Simulation illustrates a simulated pulse width of 2.70 ns that complies with the design requirement.