SNVU590A October   2018  – July 2025 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Setup
    1. 2.1 SCL/SDA Pins
    2. 2.2 NRST Pin
    3. 2.3 ENx (GPIOx) Pins
    4. 2.4 nINT
  6. 3Configuration
    1. 3.1 Configuration Sequence
    2. 3.2 Default OTP Configurations
    3. 3.3 Recommended Order of Configuring Registers Through I2C
      1. 3.3.1 Voltage Settings
      2. 3.3.2 Current Limit and Other Regulator Settings
      3. 3.3.3 GPO Settings
      4. 3.3.4 Clock Sync Functions
      5. 3.3.5 PGOOD Settings
      6. 3.3.6 Interrupt Settings
      7. 3.3.7 Startup and Shutdown Sequence
      8. 3.3.8 Set ENx Pin Control Bits
      9. 3.3.9 Set EN_BUCKx Bits
  7. 4Revision History

2.4 nINT

The nINT pin (pin 19) is an open-drain, active low output from the LP8756x-Q1 PMIC. Connect this pin to an external pullup resistor. If RESET_REG_MASK bit is unmasked, then an interrupt is generated on this pin whenever the RESET_REG_INT bit is set high. The RESET_REG_INT bit is set high when either the VANA supply voltage has decreased below the undervoltage threshold level or the host has requested a reset using the SW_RESET bit in the RESET register or device is reset by NRST. By monitoring the nINT pin, the MCU knows when the PMIC registers are reset to the default values determined by the OTP, and takes the necessary actions to make sure that the PMIC is configured as needed.

After a power-on reset, the LP8756x-Q1 PMIC requires a delay of 1.2ms before there can be any communication through the I2C interface. When the RESET_REG_MASK bit is unmasked, this required delay can be monitored through the nINT pin. After a power-on reset, the nINT pin is driven high while the registers are reset and the OTP is read to set the registers to their initial values. After 1.2ms, the nINT pin is driven low, signaling that the registers have been reset and can be configured to fit the design requirements.

Else, when RESET_REG_MASK bit is masked, nINT does not have any reaction to a power-on-reset.

Note: To monitor the nINT pin correctly, the MCU must clear all interrupts before enabling all of the outputs on the LP8756x-Q1 PMIC. Write a 1 to the RESET_REG bit in the INT_TOP2 register to clear this interrupt. If all interrupts are not cleared before enabling the LP8756x-Q1 PMIC outputs, then there is no change on the nINT pin when an interrupt is generated and the MCU is not able to detect a register reset. Make sure that the RESET_REG_MASK bit in the TOP_MASK2 register is unmasked so that an interrupt can be generated on nINT.