SNVU869 august   2023 LM5185-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Setup
    2. 2.2 Header Information
    3. 2.3 Test Points
    4. 2.4 Assembly Instructions
    5. 2.5 Best Practices
  9. 3Implementation Results
    1. 3.1 Performance Data and Results
      1. 3.1.1 Conversion Efficiency
      2. 3.1.2 Output Voltage Regulation
      3. 3.1.3 Operating Waveforms
        1. 3.1.3.1 Start-up
        2. 3.1.3.2 Load Transient Response
        3. 3.1.3.3 Switching
    2. 3.2 Thermal Performance
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials (BOM)
  11. 5Compliance Information
    1. 5.1 Compliance and Certifications
  12. 6Additional Information
    1. 6.1 Trademarks

2.2 Header Information

Table 3-1 lists the header information of the EVM.

Table 2-1 Header Information
HEADER SIGNAL DESCRIPTION
J1-1 VIN+ Voltage source input port.
J1-2 VIN- Voltage source input return.
J2 VOUT+ Output voltage port.
J3 VOUT- Output voltage return port, and also the isolated ground reference ISO-GND.
J4 PGND Primary side power ground reference.
J5-1 EN/UVLO Enable and UVLO control signal. Closing J5-1 and J5-2 disables the EVM.
J5-2 AGND Analog signal reference ground.