SPRABI1D January   2018  – July 2022 66AK2E05 , 66AK2G12 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Background
  4. 3 Migrating Designs From DDR2 to DDR3 (Features and Comparisons)
    1. 3.1 Topologies
      1. 3.1.1 Balanced Line Topology
        1. 3.1.1.1 Balanced Line Topology Issues
      2. 3.1.2 Fly-By Topology
        1. 3.1.2.1 Balanced Line Topology Issues
    2. 3.2 ECC (Error Correction)
    3. 3.3 DDR3 Features and Improvements
      1. 3.3.1 Read Leveling
      2. 3.3.2 Write Leveling
      3. 3.3.3 Pre-fetch
      4. 3.3.4 ZQ Calibration
      5. 3.3.5 Reset Pin Functionality
      6. 3.3.6 Additional DDR2 to DDR3 Differences
  5. 4 Prerequisites
    1. 4.1 High Speed Designs
    2. 4.2 JEDEC DDR3 Specification – Compatibility and Familiarity
    3. 4.3 Memory Types
    4. 4.4 Memory Speeds
    5. 4.5 Addressable Memory Space
    6. 4.6 DDR3 SDRAM/UDIMM Memories, Topologies, and Configurations
      1. 4.6.1 Topologies
      2. 4.6.2 Configurations
        1. 4.6.2.1 Memories – SDRAM Selection Criteria
    7. 4.7 DRAM Electrical Interface Requirements
      1. 4.7.1 Slew
      2. 4.7.2 Overshoot and Undershoot Specifications
        1. 4.7.2.1 Overshoot and Undershoot Example Calculations
      3. 4.7.3 Typical DDR3 AC and DC Characteristics
      4. 4.7.4 DDR3 Tolerances and Noise – Reference Signals
  6. 5 Package Selection
    1. 5.1 Summary
      1. 5.1.1 ×4 SDRAM
      2. 5.1.2 ×8 SDRAM
      3. 5.1.3 ×16 SDRAM
      4. 5.1.4 ×32 SDRAM
      5. 5.1.5 ×64 SDRAM
  7. 6 Physical Design and Implementation
    1. 6.1 Electrical Connections
      1. 6.1.1 Pin Connectivity and Unused Pins – SDRAM Examples
      2. 6.1.2 Pin Connectivity – ECC UDIMM and Non-ECC UDIMM Examples
    2. 6.2 Signal Terminations
      1. 6.2.1 External Terminations – When Using Read and Write Leveling
      2. 6.2.2 External Terminations – When Read and Write Leveling is Not Used
      3. 6.2.3 Internal Termination – On-Die Terminations
      4. 6.2.4 Active Terminations
      5. 6.2.5 Passive Terminations
      6. 6.2.6 Termination Component Selection
    3. 6.3 Mechanical Layout and Routing Considerations
      1. 6.3.1 Routing Considerations – SDRAMs
        1. 6.3.1.1  Mechanical Layout – SDRAMs
        2. 6.3.1.2  Stack Up – SDRAMs
        3. 6.3.1.3  Routing Rules – General Overview (SDRAMs)
        4. 6.3.1.4  Routing Rules – Address and Command Lines (SDRAMs)
        5. 6.3.1.5  Routing Rules – Control Lines (SDRAMs)
        6. 6.3.1.6  Routing Rules – Data Lines (SDRAMs)
        7. 6.3.1.7  Routing Rules – Clock Lines (SDRAMs)
        8. 6.3.1.8  Routing Rules – Power (SDRAMs)
        9. 6.3.1.9  Write Leveling Limit Impact on Routing – KeyStone I
        10. 6.3.1.10 Round-Trip Delay Impact on Routing – KeyStone I
        11. 6.3.1.11 Write Leveling Limit Impact on Routing – KeyStone II
        12. 6.3.1.12 Round-Trip Delay Impact on Routing – KeyStone II
      2. 6.3.2 Routing Considerations – UDIMMs
        1. 6.3.2.1 Mechanical Layout – UDIMMs
        2. 6.3.2.2 Stack Up – UDIMMs
        3. 6.3.2.3 Routing Rules – General Overview (UDIMMs)
        4. 6.3.2.4 Routing Rules – Address and Command Lines (UDIMMs)
        5. 6.3.2.5 Routing Rules – Control Lines (UDIMMs)
        6. 6.3.2.6 Routing Rules – Data Lines (UDIMMs)
        7. 6.3.2.7 Routing Rules – Clock Lines (UDIMMs)
        8. 6.3.2.8 Routing Rules – Power (UDIMMs)
        9. 6.3.2.9 Write-Leveling Limit Impact on Routing
    4. 6.4 Timing Considerations
    5. 6.5 Impedance Considerations
      1. 6.5.1 Routing Impedances – KeyStone I Devices
        1. 6.5.1.1 Data Group Signals
        2. 6.5.1.2 Fly-By Signals
      2. 6.5.2 Routing Impedances – KeyStone II Devices
        1. 6.5.2.1 Data Group Signals
        2. 6.5.2.2 Fly-By Signals
      3. 6.5.3 Comparison to JEDEC UDIMM Impedance Recommendations
    6. 6.6 Switching and Output Considerations
  8. 7 Simulation and Modeling
    1. 7.1 Simulation and Modeling
    2. 7.2 Tools
    3. 7.3 Models
    4. 7.4 TI Commitment
  9. 8 Power
    1. 8.1 DDR3 SDRAM Power Requirements
      1. 8.1.1 Vref Voltage Requirements
      2. 8.1.2 VTT Voltage Requirements
    2. 8.2 DSP DDR3 Power Requirements
    3. 8.3 DDR3 Power Estimation
    4. 8.4 DSP DDR3 Interface Power Estimation
    5. 8.5 Sequencing – DDR3 and DSP
  10. 9 Disclaimers
  11. 10References
  12. 11Revision History

6.3.1.9 Write Leveling Limit Impact on Routing – KeyStone I

The write-leveling process in the DDR3 interface imposes a limit on the maximum and minimum skew between the command delay and the data delay. If these limits are exceeded, the DDR3 interface may fail the write leveling process and data corruption may occur. These limits are sufficiently large that well-controlled topologies will not likely exceed the limits.

The command delay is defined as delay for the clock, command, control, and address group signals from the DSP to a given SDRAM. The data delay is the delay for the data group signals to that same SDRAM. The write-leveling result is effectively the difference, or skew, between these two delays.

The maximum write-leveling skew is the largest difference between the two delays in the topology to a single SDRAM. Likewise, the minimum write-leveling skew is the smallest difference between the two delays in the topology to a single SDRAM.

The write-leveling logic has a theoretical upper limit of 2500 ps. This limit does not scale with SDRAM data rate. The theoretical upper limit equates to two full clock cycles when the clock frequency is 800 MHz for DDR3-1600. It is reduced by half a clock cycle when invert clock out is enabled, as this effectively lengthens the clock by this amount.

The following set of equations provides an approximation of the maximum and minimum write-leveling skew allowed:

  • ddrclkoutperiod – period of reference clock the DSP is providing to SDRAM
  • tWLS – from JEDEC DDR3 SDRAM specification, write-leveling setup time from rising CK, CK crossing to rising DQS, DQS crossing
  • tJIT(per, lck) – clock period jitter during DLL locking period
  • commanddelay – delay for the clock, command, control and address group signals from the DSP to a given SDRAM
  • datadelay – delay for the data group signals to that same SDRAM
  • write_levelingskew – defined as the value commanddelay - datadelay
  • margin - additional margin added for preliminary use

Maximum write-leveling skew:

  • Case 1: Invert clock disabled
    • write_levelingskew < 2500 ps - tWLS - tJIT(per, lck) - margin
  • Case 2: Invert clock enabled (adds an additional half-clock period of delay to the command delay term)
    • commanddelay + (0.5 *ddrclkoutperiod) - datadelay = write_levelingskew< 2500 ps - tWLS - tJIT(per, lck) - margin
    • write_levelingskew < 2500 ps - tWLS - tJIT(per, lck) - (0.5 *ddrclkoutperiod) - margin

Minimum write-leveling skew:

  • Case 1: Invert clock disabled
    • write_levelingskew > tWLS + tJIT(per, lck) + margin
  • Case 2: Invert clock enabled (adds an additional half-clock period of delay to the command delay term)
    • commanddelay + (0.5 *ddrclkoutperiod) - datadelay = write_levelingskew > tWLS + tJIT(per, lck) + margin
    • write_levelingskew > tWLS + tJIT(per, lck) - (0.5 *ddrclkoutperiod) + margin

tWLS and tJIT(per, lck) are standard JEDEC DDR3 SDRAM timing parameters that can be obtained from the specific data sheet of the SDRAM chosen.

Note: Because this is preliminary guidance, some small margin should be subtracted from these delays to account for additional terms such as multi-rank delay skew. TI currently recommends setting the extra margin term to 100 ps.

Based on the previous equations, the following calculations and summary table shows the write-leveling skew limitations for both invert clock out enabled and disabled given the DDR3-1333 and DDR3-1600 JEDEC SDRAM specification. The first column for each speed-grade category lists the maximum write-leveling skew in picoseconds. The second column for each lists the maximum write-leveling skew in inches, assuming a signal propagation rate of 180 ps/in.

For DDR3-1333:

  • ddrclkoutperiod = 1500 ps
  • tWLS = 195 ps
  • tJIT(per, lck) = ±70 ps
  • margin = 100 ps

Maximum write-leveling skew:

  • Case 1: Invert clock disabled
    • write_levelingskew < 2500 ps - tWLS - tJIT(per, lck) - margin
    • write_levelingskew < 2500 ps - 195 ps - 70 ps -100 ps
    • write_levelingskew < 2500 ps - 195 ps - 70 ps -100 ps
    • write_levelingskew < 2135 ps
  • Case 2: Invert clock enabled (adds an additional half-clock period of delay to the command delay term)
    • write_levelingskew < 2500 ps - tWLS - tJIT(per, lck) - (0.5 *ddrclkoutperiod) - margin
    • write_levelingskew < 2500 ps - 195 ps - 70 ps - (0.5 *1500 ps) - 100 ps
    • write_levelingskew < 1385 ps

Minimum write-leveling skew:

  • Case 1: Invert Clock disabled
    • write_levelingskew > tWLS + tJIT(per, lck) + margin
    • write_levelingskew > 195 ps + 70 ps + 100 ps
    • write_levelingskew > 365 ps
  • Case 2: Invert clock enabled (adds an additional half-clock period of delay to the command delay term)
    • write_levelingskew > tWLS + tJIT(per, lck) - (0.5 *ddrclkoutperiod) + margin
    • write_levelingskew > 195 ps + 70 ps - (0.5 *1500 ps) + 100 ps
    • write_levelingskew > -385 ps
Note: This minimum write-leveling skew calculation with invert clock enabled shows how the invert clock mode can be used to correct a small amount of negative skew between the command and data groups. However, as specified in Section 6.3.1.7, all topologies should be designed for a positive skew between the command delay and data delay to avoid this situation.

For DDR3-1600:

  • ddrclkoutperiod = 1250 ps
  • tWLS = 165 ps
  • tJIT(per, lck) = ± 60 ps
  • margin = 100 ps

Maximum write-leveling skew:

  • Case 1: Invert clock disabled
    • write_levelingskew < 2500 ps - 165 ps - 60 ps -100 ps
    • write_levelingskew < 2500 ps - 165 ps - 60 ps -100 ps
    • write_levelingskew < 2175 ps
  • Case 2: Invert clock enabled (adds an additional half-clock period of delay to the command delay term)
    • write_levelingskew < 2500 ps - 165 ps - 60 ps - (0.5 *1250 ps) - 100 ps
    • write_levelingskew < 1610 ps

Minimum write-leveling skew:

  • Case 1: Invert clock disabled
    • write_levelingskew > 165 ps + 60 ps + 100 ps
    • write_levelingskew > 325 ps
  • Case 2: Invert clock enabled (adds an additional half-clock period of delay to the command delay term)
    • write_levelingskew > 165 ps + 60 ps - (0.5 *1250 ps) + 100 ps
    • write_levelingskew > -300 ps
Note: This minimum write-leveling skew calculation with invert clock enabled shows how the invert clock mode can be used to correct a small amount of negative skew between the command and data groups. However, as specified in Section 6.3.1.7, all topologies should be designed for a positive skew between the command delay and data delay to avoid this situation.
Table 6-7 Maximum Write Leveling Skew Example
Speed Grade Invert Clock Out State
Disabled Enabled
Skew in ps Skew in Inches Skew in ps Skew in Inches
DDR3-1333 2135 11.861 1385 7.694
DDR3-1600 2175 12.083 1610 8.944
Table 6-8 Minimum Write Leveling Skew Example
Speed Grade Invert Clock Out State
Disabled Enabled
Skew in ps Skew in Inches Skew in ps Skew in Inches
DDR3-1333 365 2.027 -385 2.138
DDR3-1600 325 1.805 -300 1.666
Note: Because this is preliminary guidance and some small margin should be subtracted or added from these delays to account for additional terms such as multi-rank delay skew, TI recommends that the maximum routing lengths be reduced by 10% and the minimum routing lengths be increased by 10%.