SPRAD21E May   2023  – February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 AM62x Processor Family
      1. 1.1.1 AM625
      2. 1.1.2 AM623
      3. 1.1.3 AM625SIP
      4. 1.1.4 AM625-Q1
      5. 1.1.5 AM620-Q1
    2. 1.2 AM62Ax Processor Family
      1. 1.2.1 AM62A7
      2. 1.2.2 AM62A7-Q1
      3. 1.2.3 AM62A3
      4. 1.2.4 AM62A3-Q1
    3. 1.3 AM62Px Processor Family
      1. 1.3.1 AM62P
      2. 1.3.2 AM62P-Q1
  5. 2 Related Collaterals
    1. 2.1 Links to Commonly Available and Applicable Collaterals
      1. 2.1.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1
      2. 2.1.2 AM62A7 / AM62A3
      3. 2.1.3 AM62P / AM62P-Q1
    2. 2.2 Hardware Design Guide
      1. 2.2.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1
      2. 2.2.2 AM62A7 / AM62A3
      3. 2.2.3 AM62P / AM62P-Q1
  6. 3 Processor Selection
    1. 3.1 Data Sheet
    2. 3.2 Peripheral Instance Naming Convention
    3. 3.3 Device Ordering and Quality
  7. 4 Power Architecture
    1. 4.1 Generating Supply Rails
      1. 4.1.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1
        1. 4.1.1.1 PMIC (Power Management IC)
          1. 4.1.1.1.1 Additional Reference
        2. 4.1.1.2 Discrete Power
          1. 4.1.1.2.1 DC/DC Converter
          2. 4.1.1.2.2 LDO
      2. 4.1.2 AM62A7 / AM62A3
        1. 4.1.2.1 PMIC
        2. 4.1.2.2 Discrete Power
      3. 4.1.3 AM62P / AM62P-Q1
        1. 4.1.3.1 PMIC
        2. 4.1.3.2 Discrete Power
    2. 4.2 Power Control and Protection
      1. 4.2.1 Load Switch
      2. 4.2.2 eFuse
  8. 5 General Recommendations
    1. 5.1 Processor Performance Evaluation Module (SK - Starter Kit)
    2. 5.2 Device-Specific (Processor-Specific, Processor-Family Specific) SK Versus Data Sheet
      1. 5.2.1 Notes About Component Selection
        1. 5.2.1.1 Series Resistor
        2. 5.2.1.2 Parallel Pull Resistor
        3. 5.2.1.3 Drive Strength Configuration
        4. 5.2.1.4 Data Sheet Recommendations
        5. 5.2.1.5 Processor IOs - External ESD Protection
        6. 5.2.1.6 Peripheral Clock Output Series Resistors
      2. 5.2.2 Additional Information Regarding Reuse of SK Design
        1. 5.2.2.1 Design Notes Added on the SK Schematics
        2. 5.2.2.2 SK Design Files Reuse
    3. 5.3 Before You Begin The Design
      1. 5.3.1  Documentation
      2. 5.3.2  Processor Pin Attributes (Pinout) Verification
      3. 5.3.3  Device Comparison and IOSET
      4. 5.3.4  Note on PADCONFIG Registers
      5. 5.3.5  Processor IO (Signal) Isolation for Fail-Safe Operation
      6. 5.3.6  Reference to Device-Specific SK
      7. 5.3.7  High-Speed Interface Design Guidelines
      8. 5.3.8  Recommended Current Source or Sink for LVCMOS (GPIO) Outputs
      9. 5.3.9  Connection of Slow Ramp Inputs or Capacitors to LVCMOS IOs (Inputs or Outputs)
      10. 5.3.10 Queries and Clarifications Related to Processor During Custom Board Design
  9. 6 Processor Specific Recommendations
    1. 6.1 Common (Processor Start-Up) Connection
      1. 6.1.1 Power Supply
        1. 6.1.1.1 Supply for Core and Peripherals
          1. 6.1.1.1.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 and AM62A7 / AM62A3
          2. 6.1.1.1.2 AM62P / AM62P-Q1
          3. 6.1.1.1.3 Additional Information
        2. 6.1.1.2 Supply for IO Groups
          1. 6.1.1.2.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 and AM62A7 / AM62A3
          2. 6.1.1.2.2 AM62P / AM62P-Q1
          3. 6.1.1.2.3 Additional Information
        3. 6.1.1.3 Supply for VPP (eFuse ROM Programming)
        4. 6.1.1.4 Supply Connection for Partial IO Mode (Low Power) Configuration
          1. 6.1.1.4.1 Partial IO Used
          2. 6.1.1.4.2 Partial IO Not Used
          3. 6.1.1.4.3 Data Sheet Reference for Power Sequence
        5. 6.1.1.5 Additional Information
      2. 6.1.2 Capacitors for Supply Rails
        1. 6.1.2.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1
        2. 6.1.2.2 AM62A7 / AM62A3 and AM62P / AM62P-Q1
        3. 6.1.2.3 Additional Information
          1. 6.1.2.3.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 and AM62A7 / AM62A3
          2. 6.1.2.3.2 AM62P / AM62P-Q1
      3. 6.1.3 Processor Clock
        1. 6.1.3.1 Clock Inputs
          1. 6.1.3.1.1 High Frequency Oscillator (MCU_OSC0_XI/ MCU_OSC0_XO)
          2. 6.1.3.1.2 Low Frequency Oscillator (WKUP_LFOSC0_XI/ WKUP_LFOSC0_XO)
          3. 6.1.3.1.3 EXT_REFCLK1 (External Clock Input to Main Domain)
          4. 6.1.3.1.4 Additional Information
        2. 6.1.3.2 Clock Outputs
      4. 6.1.4 Processor Reset
        1. 6.1.4.1 External Reset Inputs
        2. 6.1.4.2 External Reset Status Outputs
        3. 6.1.4.3 Additional Information
      5. 6.1.5 Configuration of Boot Modes (for Processor)
        1. 6.1.5.1 Processor Boot Mode Inputs Isolation Buffers Use Case and Optimization
        2. 6.1.5.2 Bootmode Selection
          1. 6.1.5.2.1 Notes for USB Boot Mode
        3. 6.1.5.3 Additional Information
    2. 6.2 Board Debug Using JTAG and EMU
      1. 6.2.1 Additional Information
  10. 7 Processor Peripherals
    1. 7.1 Supply Connections for IO Groups
      1. 7.1.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 and AM62A7 / AM62A3
      2. 7.1.2 AM62P / AM62P-Q1
    2. 7.2 Memory Interface (DDRSS (DDR4 / LPDDR4), MMCSD (eMMC / SD / SDIO), OSPI / QSPI and GPMC)
      1. 7.2.1 DDR Subsystem (DDRSS)
        1. 7.2.1.1 DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.1.1 AM625 / AM623 / AM625-Q1 / AM620-Q1
            1. 7.2.1.1.1.1 Interface Configuration
            2. 7.2.1.1.1.2 Routing Topology and Terminations
            3. 7.2.1.1.1.3 Resistors for Control and Calibration
            4. 7.2.1.1.1.4 Capacitors for the Power Supply Rails
            5. 7.2.1.1.1.5 Data Bit or Byte Swapping
            6. 7.2.1.1.1.6 VTT Termination Schematics Reference
          2. 7.2.1.1.2 AM625SIP
          3. 7.2.1.1.3 AM62A7 / AM62A3
          4. 7.2.1.1.4 AM62P / AM62P-Q1
        2. 7.2.1.2 LPDDR4 SDRAM (Low-Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.2.1 AM625 / AM623 / AM625-Q1 / AM620-Q1
            1. 7.2.1.2.1.1 Interface Configuration
            2. 7.2.1.2.1.2 Routing Topology and Terminations
            3. 7.2.1.2.1.3 Resistors for Control and Calibration
            4. 7.2.1.2.1.4 Capacitors for the Power Supply Rails
            5. 7.2.1.2.1.5 Data Bit or Byte Swapping
          2. 7.2.1.2.2 AM625SIP
          3. 7.2.1.2.3 AM62A7 / AM62A3 and AM62P / AM62P-Q1
            1. 7.2.1.2.3.1 Interface Configuration
            2. 7.2.1.2.3.2 Routing Topology and Terminations
            3. 7.2.1.2.3.3 Resistors for Control and Calibration
            4. 7.2.1.2.3.4 Capacitors for the Power Supply Rails
            5. 7.2.1.2.3.5 Data Bit or Byte Swapping
      2. 7.2.2 Multi-Media Card/Secure Digital (MMCSD)
        1. 7.2.2.1 MMC0 - eMMC (Embedded Multi-Media Card) Interface
          1. 7.2.2.1.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 and AM62A7 / AM62A3
            1. 7.2.2.1.1.1 IO Power Supply
            2. 7.2.2.1.1.2 eMMC (Attached Device) Reset
            3. 7.2.2.1.1.3 Signals Termination
            4. 7.2.2.1.1.4 Capacitors for the Power Supply Rails
          2. 7.2.2.1.2 AM62P / AM62P-Q1
            1. 7.2.2.1.2.1 MMC0 Used
              1. 7.2.2.1.2.1.1 IO Power Supply
              2. 7.2.2.1.2.1.2 eMMC (Attached Device) Reset
              3. 7.2.2.1.2.1.3 Signals Termination
              4. 7.2.2.1.2.1.4 Capacitors for the Power Supply Rails
            2. 7.2.2.1.2.2 MMC0 Not Used
          3. 7.2.2.1.3 Additional Information on eMMC PHY
        2. 7.2.2.2 MMC0 – SD (Secure Digital) Card Interface
        3. 7.2.2.3 MMC1 / MMC2 – SD (Secure Digital) Card Interface
          1. 7.2.2.3.1 IO Power Supply
          2. 7.2.2.3.2 SD Card Supply Reset and Boot Configuration
          3. 7.2.2.3.3 Signals Termination
          4. 7.2.2.3.4 ESD Protection
          5. 7.2.2.3.5 Capacitors for the Power Supply Rails
        4. 7.2.2.4 Additional Information
      3. 7.2.3 Octal Serial Peripheral Interface (OSPI) and Quad Serial Peripheral Interface (QSPI)
        1. 7.2.3.1 IO Power Supply
        2. 7.2.3.2 OSPI / QSPI Reset
        3. 7.2.3.3 Signals Termination
        4. 7.2.3.4 Loopback Clock
        5. 7.2.3.5 Interface to Multiple Devices
        6. 7.2.3.6 Capacitors for the Power Supply Rails
      4. 7.2.4 General-Purpose Memory Controller (GPMC)
        1. 7.2.4.1 IO Power Supply
        2. 7.2.4.2 GPMC Interface
        3. 7.2.4.3 Memory (Attached Device) Reset
        4. 7.2.4.4 Signals Termination
          1. 7.2.4.4.1 GPMC NAND
        5. 7.2.4.5 Capacitors for the Power Supply Rails
    3. 7.3 External Communication Interface (Ethernet (CPSW3G), USB2.0, PRUSS, UART and CAN)
      1. 7.3.1 Ethernet Interface Using CPSW3G (Common Platform Ethernet Switch 3-Port Gigabit)
        1. 7.3.1.1 IO Power Supply
        2. 7.3.1.2 Ethernet PHY Reset
        3. 7.3.1.3 Ethernet PHY Pin Strapping
        4. 7.3.1.4 Ethernet PHY (and MAC) Operation and Media Independent Interface (MII) Clock
          1. 7.3.1.4.1 Crystal
          2. 7.3.1.4.2 Oscillator
          3. 7.3.1.4.3 Processor Clock Output (CLKOUT0)
        5. 7.3.1.5 MAC (Data, Control and Clock) Interface Signals Termination
        6. 7.3.1.6 MAC (Media Access Controller) to MAC Interface
        7. 7.3.1.7 MDIO (Management Data Input/Output) Interface
        8. 7.3.1.8 Ethernet MDI (Medium Dependent Interface) Including Magnetics
        9. 7.3.1.9 Capacitors for the Power Supply Rails
      2. 7.3.2 Universal Serial Bus (USB2.0)
        1. 7.3.2.1 USBn (0..1) Used
          1. 7.3.2.1.1 USB Host Interface
          2. 7.3.2.1.2 USB Device Interface
          3. 7.3.2.1.3 USB Dual-Role-Device Interface
          4. 7.3.2.1.4 USB Type-C
        2. 7.3.2.2 USBn (0..1) Not Used
        3. 7.3.2.3 Additional Information
      3. 7.3.3 Programmable Real-Time Unit Subsystem (PRUSS)
        1. 7.3.3.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1
        2. 7.3.3.2 AM62A7 / AM62A3 and AM62P / AM62P-Q1
      4. 7.3.4 Universal Asynchronous Receiver/Transmitter (UART)
      5. 7.3.5 Controller Area Network (CAN)
    4. 7.4 On-Board Synchronous Communication Interface (MCSPI, MCASP and I2C)
      1. 7.4.1 Multichannel Serial Peripheral Interface (MCSPI) and Multichannel Audio Serial Ports (MCASP)
      2. 7.4.2 Inter-Integrated Circuit (I2C)
    5. 7.5 User Interface (CSIRX0, DPI, OLDI, DSI), GPIO and Hardware Diagnostics
      1. 7.5.1 Camera Serial Interface (CSI-Rx (CSI-2 port, CSIRX0 Instance))
        1. 7.5.1.1 CSIRX0 Used
        2. 7.5.1.2 CSIRX0 Not Used
      2. 7.5.2 Display Subsystem
        1. 7.5.2.1 Display Parallel Interface (DPI)
          1. 7.5.2.1.1 AM625 / AM623 / AM625SIP / AM625-Q1 and AM62A7 / AM62A3 and AM62P / AM62P-Q1
            1. 7.5.2.1.1.1 IO Power Supply
            2. 7.5.2.1.1.2 DPI (Attached Device) Reset
            3. 7.5.2.1.1.3 Connection
            4. 7.5.2.1.1.4 Signals Termination
            5. 7.5.2.1.1.5 Capacitors for the Power Supply Rails
          2. 7.5.2.1.2 AM620-Q1
        2. 7.5.2.2 Open LVDS Display Interface (OLDI)
          1. 7.5.2.2.1 AM625 / AM623 / AM625SIP / AM625-Q1 and AM62P / AM62P-Q1
            1. 7.5.2.2.1.1 OLDI0 Used
              1. 7.5.2.2.1.1.1 IO Power Supply
              2. 7.5.2.2.1.1.2 OLDI (Attached Device) Reset
              3. 7.5.2.2.1.1.3 OLDI Interface Compatibility
              4. 7.5.2.2.1.1.4 Capacitors for the Power Supply Rails
            2. 7.5.2.2.1.2 OLDI0 Not Used
            3. 7.5.2.2.1.3 Additional Information
          2. 7.5.2.2.2 AM620-Q1 and AM62A7 / AM62A3
        3. 7.5.2.3 Display Serial Interface (DSI)
          1. 7.5.2.3.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 and AM62A7 / AM62A3
          2. 7.5.2.3.2 AM62P / AM62P-Q1
            1. 7.5.2.3.2.1 DSITX0 Used
            2. 7.5.2.3.2.2 DSITX0 Not Used
      3. 7.5.3 General Purpose Input/Output (GPIO)
        1. 7.5.3.1 CLKOUT Available on GPIO
        2. 7.5.3.2 Connection and External Buffering
        3. 7.5.3.3 Additional Information
      4. 7.5.4 On-board Hardware Diagnostics
        1. 7.5.4.1 Monitoring of On-Board Supply Voltages Using Processor
          1. 7.5.4.1.1 Voltage Monitor Pins Used
          2. 7.5.4.1.2 Voltage Monitor Pins Not Used
        2. 7.5.4.2 Internal Temperature Monitoring
        3. 7.5.4.3 Connection of Error Signal Output (MCU_ERRORn)
        4. 7.5.4.4 High Frequency Oscillator (MCU_OSC0) Clock Loss Detection
    6. 7.6 Verifying Board Level Design Issues
      1. 7.6.1 Processor Pin Configuration Using Pinmux Tool
      2. 7.6.2 Schematics Configurations
      3. 7.6.3 Connecting Supply Rails to Pullups
      4. 7.6.4 Peripheral (Sub System) Clock Outputs
      5. 7.6.5 General Debug
        1. 7.6.5.1 Clock Output for Board Bring-Up, Test or Debug
        2. 7.6.5.2 Additional Information
  11. 8 Layout Notes (Added on the Schematic)
  12. 9 Custom Board Design Simulation
  13. 10Additional References
    1. 10.1 FAQ Covering AM6xx Processor Family
    2. 10.2 FAQs - Processor Product Family Wise
    3. 10.3 Processor Attached Devices
  14. 11Summary
  15. 12References
    1. 12.1 AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1
    2. 12.2 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
    3. 12.3 AM62P / AM62P-Q1
    4. 12.4 Common for all Family of Processors
    5. 12.5 Master List of Available FAQs - Processor Family Wise
    6. 12.6 FAQs Including Software Related FAQs
    7. 12.7 FAQs for Attached Devices
  16. 13Terminology
  17. 14Revision History

6.1.5 Configuration of Boot Modes (for Processor)

Boot mode inputs do not have internal pullup or pulldown resistors that are active during processor power-up or reset. It is recommended to connect external pullup or pulldown resistors to set the required boot mode.

When dip switches are used, it is recommended to use a resistor divider ratio of 470 Ω (pullup) and 47 kΩ (pulldown) for improved noise performance.

When the bootmode is configured using only resistors, a standard resistor (same value for pullup or pulldown) value Example: 10 kΩ or similar is recommended since either the pullup or pulldown resistor will be used.

It is recommended to connect pullup or pulldown resistor to boot mode pins marked as Reserved or not used.

BOOTMODE 14 and BOOTMODE 15 pins are Reserved for AM62x family of processors.

BOOTMODE 14 and BOOTMODE 15 pins are Reserved for AM62Ax family of processors.

BOOTMODE 14 pin is Reserved and BOOTMODE 15 pin is POST (Hardware Power-on-Self-test) functionality for AM62Px family of processors. It is recommended to add provision for pullup and pulldown resistors for BOOTMODE 15 pin.

It is highly recommended to add provision for pullup and pulldown resistors for all the boot mode pins that have configuration capability for debugging, design flexibility and future enhancement. Populate either pullup or pulldown for each boot mode pins. Direct connection of boot mode pins to ground or IO supply rail is not recommended or allowed since these IOs have alternate configuration and could intentionally or unintentionally be configured as output by the software.

Boot mode input pins are not fail-safe and this needs to be considered when boot mode configurations are being driven from an external input or a base board.

Based on the application requirement, a buffer that is driven only when reset (MCU_PORz) is asserted (low) can be used to present the boot configuration to the processor.

If the bootmode pins are configured as an output during normal operation, a series resistor (~1 kΩ) is recommended at the output of the buffers. For more information, see the device-specific SK for implementation.