SPRUGR9H November   2010  – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678

 

  1.   Preface
    1.     About This Manual
    2.     Trademarks
    3.     Notational Conventions
    4.     Related Documentation from Texas Instruments
  2. 1Introduction
    1. 1.1  Terminology Used in This Document
    2. 1.2  KeyStone I Features
    3. 1.3  KeyStone I Functional Block Diagram
    4. 1.4  KeyStone II Changes to QMSS
    5. 1.5  KeyStone II QMSS Modes of Use
      1. 1.5.1 Shared Mode
      2. 1.5.2 Split Mode
    6. 1.6  Overview
    7. 1.7  Queue Manager
    8. 1.8  Packet DMA (PKTDMA)
    9. 1.9  Navigator Cloud
    10. 1.10 Virtualization
    11. 1.11 ARM-DSP Shared Use
    12. 1.12 PDSP Firmware
  3. 2Operational Concepts
    1. 2.1 Packets
    2. 2.2 Queues
      1. 2.2.1 Packet Queuing
      2. 2.2.2 Packet De-queuing
      3. 2.2.3 Queue Proxy
    3. 2.3 Queue Types
      1. 2.3.1 Transmit Queues
      2. 2.3.2 Transmit Completion Queues
      3. 2.3.3 Receive Queues
      4. 2.3.4 Free Descriptor Queues (FDQ)
        1. 2.3.4.1 Host Packet Free Descriptors
        2. 2.3.4.2 Monolithic Free Descriptors
      5. 2.3.5 Queue Pend Queues
    4. 2.4 Descriptors
      1. 2.4.1 Host Packet
      2. 2.4.2 Host Buffer
      3. 2.4.3 Monolithic Packet
    5. 2.5 Packet DMA
      1. 2.5.1 Channels
      2. 2.5.2 RX Flows
    6. 2.6 Packet Transmission Overview
    7. 2.7 Packet Reception Overview
    8. 2.8 ARM Endianess
  4. 3Descriptor Layouts
    1. 3.1 Host Packet Descriptor
    2. 3.2 Host Buffer Descriptor
    3. 3.3 Monolithic Descriptor
  5. 4Registers
    1. 4.1 Queue Manager
      1. 4.1.1 Queue Configuration Region
        1. 4.1.1.1 Revision Register (0x00000000)
        2. 4.1.1.2 Queue Diversion Register (0x00000008)
        3. 4.1.1.3 Linking RAM Region 0 Base Address Register (0x0000000C)
        4. 4.1.1.4 Linking RAM Region 0 Size Register (0x00000010)
        5. 4.1.1.5 Linking RAM Region 1 Base Address Register (0x00000014)
        6. 4.1.1.6 Free Descriptor/Buffer Starvation Count Register N (0x00000020 + N×4)
      2. 4.1.2 Queue Status RAM
      3. 4.1.3 Descriptor Memory Setup Region
        1. 4.1.3.1 Memory Region R Base Address Register (0x00000000 + 16×R)
        2. 4.1.3.2 Memory Region R Start Index Register (0x00000004 + 16×R)
        3. 4.1.3.3 Memory Region R Descriptor Setup Register (0x00000008 + 16×R)
      4. 4.1.4 Queue Management/Queue Proxy Regions
        1. 4.1.4.1 Queue N Register A (0x00000000 + 16×N)
        2. 4.1.4.2 Queue N Register B (0x00000004 + 16×N)
        3. 4.1.4.3 Queue N Register C (0x00000008 + 16×N)
        4. 4.1.4.4 Queue N Register D (0x0000000C + 16×N)
      5. 4.1.5 Queue Peek Region
        1. 4.1.5.1 Queue N Status and Configuration Register A (0x00000000 + 16×N)
        2. 4.1.5.2 Queue N Status and Configuration Register B (0x00000004 + 16×N)
        3. 4.1.5.3 Queue N Status and Configuration Register C (0x00000008 + 16×N)
        4. 4.1.5.4 Queue N Status and Configuration Register D (0x0000000C + 16×N)
    2. 4.2 Packet DMA
      1. 4.2.1 Global Control Registers Region
        1. 4.2.1.1 Revision Register (0x00)
        2. 4.2.1.2 Performance Control Register (0x04)
        3. 4.2.1.3 Emulation Control Register (0x08)
        4. 4.2.1.4 Priority Control Register (0x0C)
        5. 4.2.1.5 QMn Base Address Register (0x10, 0x14, 0x18, 0x1c)
      2. 4.2.2 TX DMA Channel Configuration Region
        1. 4.2.2.1 TX Channel N Global Configuration Register A (0x000 + 32×N)
        2. 4.2.2.2 TX Channel N Global Configuration Register B (0x004 + 32×N)
      3. 4.2.3 RX DMA Channel Configuration Region
        1. 4.2.3.1 RX Channel N Global Configuration Register A (0x000 + 32×N)
      4. 4.2.4 RX DMA Flow Configuration Region
        1. 4.2.4.1 RX Flow N Configuration Register A (0x000 + 32×N)
        2. 4.2.4.2 RX Flow N Configuration Register B (0x004 + 32×N)
        3. 4.2.4.3 RX Flow N Configuration Register C (0x008 + 32×N)
        4. 4.2.4.4 RX Flow N Configuration Register D (0x00C + 32×N)
        5. 4.2.4.5 RX Flow N Configuration Register E (0x010 + 32×N)
        6. 4.2.4.6 RX Flow N Configuration Register F (0x014 + 32×N)
        7. 4.2.4.7 RX Flow N Configuration Register G (0x018 + 32×N)
        8. 4.2.4.8 RX Flow N Configuration Register H (0x01C + 32×N)
      5. 4.2.5 TX Scheduler Configuration Region
        1. 4.2.5.1 TX Channel N Scheduler Configuration Register (0x000 + 4×N)
    3. 4.3 QMSS PDSPs
      1. 4.3.1 Descriptor Accumulation Firmware
        1. 4.3.1.1 Command Buffer Interface
        2. 4.3.1.2 Global Timer Command Interface
        3. 4.3.1.3 Reclamation Queue Command Interface
        4. 4.3.1.4 Queue Diversion Command Interface
      2. 4.3.2 Quality of Service Firmware
        1. 4.3.2.1 QoS Algorithms
          1. 4.3.2.1.1 Modified Token Bucket Algorithm
        2. 4.3.2.2 Command Buffer Interface
        3. 4.3.2.3 QoS Firmware Commands
        4. 4.3.2.4 QoS Queue Record
        5. 4.3.2.5 QoS Cluster Record
        6. 4.3.2.6 RR-Mode QoS Cluster Record
        7. 4.3.2.7 SRIO Queue Monitoring
          1. 4.3.2.7.1 QoS SRIO Queue Monitoring Record
      3. 4.3.3 Open Event Machine Firmware
      4. 4.3.4 Interrupt Operation
        1. 4.3.4.1 Interrupt Handshaking
        2. 4.3.4.2 Interrupt Processing
        3. 4.3.4.3 Interrupt Generation
        4. 4.3.4.4 Stall Avoidance
      5. 4.3.5 QMSS PDSP Registers
        1. 4.3.5.1 Control Register (0x00000000)
        2. 4.3.5.2 Status Register (0x00000004)
        3. 4.3.5.3 Cycle Count Register (0x0000000C)
        4. 4.3.5.4 Stall Count Register (0x00000010)
    4. 4.4 QMSS Interrupt Distributor
      1. 4.4.1 INTD Register Region
        1. 4.4.1.1  Revision Register (0x00000000)
        2. 4.4.1.2  End Of Interrupt (EOI) Register (0x00000010)
        3. 4.4.1.3  Status Register 0 (0x00000200)
        4. 4.4.1.4  Status Register 1 (0x00000204)
        5. 4.4.1.5  Status Register 2 (0x00000208)
        6. 4.4.1.6  Status Register 3 (0x0000020c)
        7. 4.4.1.7  Status Register 4 (0x00000210)
        8. 4.4.1.8  Status Clear Register 0 (0x00000280)
        9. 4.4.1.9  Status Clear Register 1 (0x00000284)
        10. 4.4.1.10 Status Clear Register 4 (0x00000290)
        11. 4.4.1.11 Interrupt N Count Register (0x00000300 + 4xN)
  6. 5Mapping Information
    1. 5.1 Queue Maps
    2. 5.2 Interrupt Maps
      1. 5.2.1 KeyStone I TCI661x, C6670, C665x devices
      2. 5.2.2 KeyStone I TCI660x, C667x devices
      3. 5.2.3 KeyStone II devices
    3. 5.3 Memory Maps
      1. 5.3.1 QMSS Register Memory Map
      2. 5.3.2 KeyStone I PKTDMA Register Memory Map
      3. 5.3.3 KeyStone II PKTDMA Register Memory Map
    4. 5.4 Packet DMA Channel Map
  7. 6Programming Information
    1. 6.1 Programming Considerations
      1. 6.1.1 System Planning
      2. 6.1.2 Notification of Completed Work
    2. 6.2 Example Code
      1. 6.2.1 QMSS Initialization
      2. 6.2.2 PKTDMA Initialization
      3. 6.2.3 Normal Infrastructure DMA with Accumulation
      4. 6.2.4 Bypass Infrastructure notification with Accumulation
      5. 6.2.5 Channel Teardown
    3. 6.3 Programming Overrides
    4. 6.4 Programming Errors
    5. 6.5 Questions and Answers
  8. AExample Code Utility Functions
  9. BExample Code Types
  10. CExample Code Addresses
    1. C.1 KeyStone I Addresses:
    2. C.2 KeyStone II Addresses:
  11.   Revision History

4.2.4.3 RX Flow N Configuration Register C (0x008 + 32×N)

The RX Flow N Configuration Register C contains static configuration information for the RX DMA flow. The fields in this register can be safely changed only when all of the DMA channels that use this flow have been disabled. The fields in this register are shown in Figure 4-29:

Figure 4-29 RX Flow N Configuration Register C (0x008 + 32×N)
31 30 28 27 26 24 23 22 20
Reserved RX_SRC_TAG_HI_SEL Reserved RX_SRC_TAG_LO_SEL Reserved RX_DEST_TAG_HI_SEL
R-0 W-0 R-0 W-0 R-0 W-0
19 18 16 15 3 2 0
Reserved RX_DEST_TAG_LO_SEL Reserved RX_SIZE_THRESH_EN
R-0 W-0 R-0 W-0
Legend: R = Read only; W = Write only; - n = value after reset

Table 4-37 RX Flow N Configuration Register C Field Descriptions

Bit Field Description
31 Reserved Reads return 0 and writes have no effect.
30-28 RX_SRC_TAG_HI_SEL RX source tag high byte selector. This field specifies the source for bits 31-24 of the source tag field in the output packet descriptor. This field is encoded as follows:
  • 0 = Do not overwrite
  • 1 = Overwrite with value given in RX_SRC_TAG_HI
  • 2 = Overwrite with flow_id from back end application
  • 3 = Reserved
  • 4 = Overwrite with src_tag from back end application
  • 5 = Reserved
  • 6-7 = Reserved
27 Reserved Reads return 0 and writes have no effect.
26-24 RX_SRC_TAG_LO_SEL RX source tag low byte selector. This field specifies the source for bits 23-16 of the source tag field in the output packet descriptor. This field is encoded as follows:
  • 0 = Do not overwrite
  • 1 = Overwrite with value given in RX_SRC_TAG_LO
  • 2 = Overwrite with flow_id from back end application
  • 3 = Reserved
  • 4 = Overwrite with src_tag from back end application
  • 5 = Reserved
  • 6-7 = Reserved
23 Reserved Reads return 0 and writes have no effect.
22-20 RX_DEST_TAG_HI_SEL RX destination tag high byte selector. This field specifies the source for bits 15-8 of the source tag field in the word 1 of the output PD. This field is encoded as follows:
  • 0 = Do not overwrite
  • 1 = Overwrite with value given in RX_DEST_TAG_HI
  • 2 = Overwrite with flow_id from back end application
  • 3 = Reserved
  • 4 = Overwrite with dest_tag[7-0] from back end application
  • 5 = Overwrite with dest_tag[15-8] from back end application
  • 6-7 = Reserved
19 Reserved Reads return 0 and writes have no effect.
18-16 RX_DEST_TAG_LO_SEL RX destination tag low byte selector. This field specifies the source for bits 7-0 of the source tag field in word 1 of the output PD. This field is encoded as follows:
  • 0 = Do not overwrite
  • 1 = Overwrite with value given in RX_DEST_TAG_LO
  • 2 = Overwrite with flow_id from back end application
  • 3 = Reserved
  • 4 = Overwrite with dest_tag[7-0] from back end application
  • 5 = Overwrite with dest_tag[15-8] from back end application
  • 6-7 = Reserved
15-3 Reserved Reads return 0 and writes have no effect.
2-0 RX_SIZE_THRESH_EN RX packet sized based free buffer queue enables. These bits control whether or not the flow will compare the packet size received from the back end application against the RX_SIZE_THRESHN fields to determine which FDQ to allocate the SOP buffer from. Each bit in this field corresponds to 1 of the 3 potential size thresholds that can be compared against. Bit 0 corresponds to RX_SIZE_THRESH0 and bit 2 corresponds to RX_SIZE_THRESH2.

The bits in this field are encoded as follows:

  • 0 = Do not use the threshold.
  • 1 = Use the thresholds to select between the 4 different potential SOP FDQs.

If thresholds are to be used, the thresholds must be used starting at 0 and progressing to 2. If a single threshold is required, threshold 0 must be used. If 2 thresholds are required, 0 and 1 must be used. It is illegal to enable a higher threshold without enabling the lower thresholds. The following values are valid:

  • 0 - no thresholds enabled.
  • 1 - threshold 0 enabled, implies RX_FDQ0_SZ0,1_QNUM,QMGR are used.
  • 3 - thresholds 0, 1 enabled, implies RX_FDQ0_SZ0,1,2_QNUM,QMGR are used.
  • 7 - thresholds 0, 1, 2 enabled, implies RX_FDQ0_SZ0,1,2,3_QNUM,QMGR are used.

If none of the thresholds are enabled, the DMA controller in the port will allocate the SOP buffer from the queue specified by the RX_FDQ0_SZ0_QMGR and RX_FDQ0_SZ0_QNUM fields. Support for packet size based FDQ selection is optional. If the port does not implement this feature, the bits of this field will be hardcoded to 0 and will not be writable by the host.

NOTE: This functionality is available only if supported by the particular peripheral. The usual limitation is that the peripheral doesn’t have packet size information available for the SOP transaction, which is when FDQ selection must be performed. Examples of this feature not being available are: AIF2, BCP, and SRIO Type 9 messages.