SPRUIY2A November   2024  – March 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1Architecture Overview
    1. 1.1 Introduction to the CPU
    2. 1.2 Data Type
    3. 1.3 C29x CPU System Architecture
      1. 1.3.1 Emulation Logic
      2. 1.3.2 CPU Interface Buses
    4. 1.4 Memory Map
  4. 2Central Processing Unit (CPU)
    1. 2.1 C29x CPU Architecture
      1. 2.1.1 Features
      2. 2.1.2 Block Diagram
    2. 2.2 CPU Registers
      1. 2.2.1 Addressing Registers (Ax/XAx)
      2. 2.2.2 Fixed-Point Registers (Dx/XDx)
      3. 2.2.3 Floating-Point Register (Mx/XMx)
      4. 2.2.4 Program Counter (PC)
      5. 2.2.5 Return Program Counter (RPC)
      6. 2.2.6 Status Registers
        1. 2.2.6.1 Interrupt Status Register (ISTS)
        2. 2.2.6.2 Decode Phase Status Register (DSTS)
        3. 2.2.6.3 Execute Phase Status Register (ESTS)
    3. 2.3 Instruction Packing
      1. 2.3.1 Standalone Instructions and Restrictions
      2. 2.3.2 Instruction Timeout
    4. 2.4 Stacks
      1. 2.4.1 Software Stack
      2. 2.4.2 Protected Call Stack
      3. 2.4.3 Real Time Interrupt / NMI Stack
  5. 3Interrupts
    1. 3.1 CPU Interrupts Architecture Block Diagram
    2. 3.2 RESET, NMI, RTINT, and INT
      1. 3.2.1 RESET (CPU reset)
        1. 3.2.1.1 Required Instructions (RESET)
      2. 3.2.2 NMI (Non-Maskable Interrupt)
        1. 3.2.2.1 Blocking and Masking (NMI)
        2. 3.2.2.2 Signal Propagation (NMI)
        3. 3.2.2.3 Stack (NMI)
        4. 3.2.2.4 Required Instructions (NMI)
      3. 3.2.3 RTINT (Real-Time Interrupt)
        1. 3.2.3.1 Blocking and Masking (RTINT)
        2. 3.2.3.2 Signal Propagation (RTINT)
        3. 3.2.3.3 Stack (RTINT)
        4. 3.2.3.4 Required Instructions (RTINT)
      4. 3.2.4 INT (Low-Priority Interrupt)
        1. 3.2.4.1 Blocking and Masking (INT)
        2. 3.2.4.2 Signal Propagation (INT)
        3. 3.2.4.3 Stack (INT)
    3. 3.3 Conditions Blocking Interrupts
      1. 3.3.1 ATOMIC Counter
    4. 3.4 CPU Interrupt Control Registers
      1. 3.4.1 Interrupt Status Register (ISTS)
      2. 3.4.2 Decode Phase Status Register (DSTS)
      3. 3.4.3 Interrupt-Related Stack Registers
    5. 3.5 Interrupt Nesting
      1. 3.5.1 Interrupt Nesting Example Diagram
    6. 3.6 Security
      1. 3.6.1 Overview
      2. 3.6.2 LINK
      3. 3.6.3 STACK
      4. 3.6.4 ZONE
  6. 4Addressing Modes
    1. 4.1 Addressing Modes Overview
      1. 4.1.1 Documentation and Implementation
      2. 4.1.2 List of Addressing Mode Types
        1. 4.1.2.1 Additional Types of Addressing
      3. 4.1.3 Addressing Modes Summarized
    2. 4.2 Addressing Mode Fields
      1. 4.2.1 ADDR1 Field
      2. 4.2.2 ADDR2 Field
      3. 4.2.3 ADDR3 Field
      4. 4.2.4 DIRM Field
      5. 4.2.5 Additional Fields
    3. 4.3 Alignment and Pipeline Considerations
      1. 4.3.1 Alignment
      2. 4.3.2 Pipeline Considerations
    4. 4.4 Types of Addressing Modes
      1. 4.4.1 Direct Addressing
      2. 4.4.2 Pointer Addressing
        1. 4.4.2.1 Pointer Addressing with #Immediate Offset
        2. 4.4.2.2 Pointer Addressing with Pointer Offset
        3. 4.4.2.3 Pointer Addressing with #Immediate Increment/Decrement
        4. 4.4.2.4 Pointer Addressing with Pointer Increment/Decrement
      3. 4.4.3 Stack Addressing
        1. 4.4.3.1 Allocating and De-allocating Stack Space
      4. 4.4.4 Circular Addressing Instruction
      5. 4.4.5 Bit Reversed Addressing Instruction
  7. 5Safety and Security Unit (SSU)
    1. 5.1 SSU Overview
    2. 5.2 Links and Task Isolation
    3. 5.3 Sharing Data Outside Task Isolation Boundary
    4. 5.4 Protected Call and Return
  8. 6Emulation
    1. 6.1 Overview of Emulation Features
    2. 6.2 Debug Terminology
    3. 6.3 Debug Interface
    4. 6.4 Execution Control Mode
    5. 6.5 Breakpoints, Watchpoints, and Counters
      1. 6.5.1 Software Breakpoint
      2. 6.5.2 Hardware Debugging Resources
        1. 6.5.2.1 Hardware Breakpoint
        2. 6.5.2.2 Hardware Watchpoint
        3. 6.5.2.3 Benchmark Counters
      3. 6.5.3 PC Trace
  9. 7Revision History

4.2.2 ADDR2 Field

This is a 5-bit field for indirect encoding of addresses that can be used in all "Pointer Addressing" modes.

Table 4-3 shows the various ways the 5 bits can be used to encode the address.

Table 4-3 ADDR2 Field Encodings
ADDR2 Field: (Az = A4 to A7)
Mnemonic Shorthand Address Generation 4 3 2 1 0
*(Az++A0) *Az++A0 addr = Az, Az = Az + A0 0 0 0 Az[4-7]
*(Az++A1) *Az++A1 addr = Az, Az = Az + A1 0 0 1 Az[4-7]
*(Az+A0<<#scale) *Az[A0] addr = Az + A0 << (0/1/2/3) (1) 0 1 0 Az[4-7]
*(Az+A1<<#scale) *Az[A1] addr = Az + A1 << (0/1/2/3) (1) 0 1 1 Az[4-7]
*Az *Az addr = Az 1 0 0 Az[4-7]
*(Az++#size) *Az++ addr = Az, Az = Az + (1/2/4/8) (#size = 1,2,4,8) (1) 1 0 1 Az[4-7]
*(Az--#size) *Az-- addr = Az, Az = Az – (1/2/4/8) (#size = 1,2,4,8) (1) 1 1 0 Az[4-7]
*(Az-=#size) *--Az Az = Az – (1/2/4/8), addr = Az (#size = 1,2,4,8) (1) 1 1 1 Az[4-7]
Note: The ADDR2 opcode field modes do not specify the increment step size ("#size") or scale amount ("#scale"). This is automatically performed by the CPU hardware based on the word size being accessed by the instruction.
  • Byte access increments/decrements by #size=1, or scales by #scale=0 (multiply by 1)
  • 16-bit access increments/decrements by #size=2, or scales by #scale=1 (multiply by 2)
  • 32-bit access increments/decrements by #size=4, or scales by #scale=2 (multiply by 4)
  • 64-bit access increments/decrements by #size=8, or scales by #scale=3 (multiply by 8)

The following are the instructions that can use the ADDR2 field:

AND.32, ANDOR, LD.32, LD.64, MV.16, MV.32, MV.64, MV.8, OR.32, ST.16, ST.32, ST.64, ST.8, XOR.32

Examples:

; Register XMx is loaded with the 64-bit word at the memory location 
; addressed using the ADDR2 addressing mode. This address is fetched from Az.
LD.64 XMx,ADDR2             ; field
LD.64 XMx,*Az               ; addressing mode
LD.64 XM4,*A4               ; actual assembly code

; The 8-bit immediate value specified is stored at the memory location 
; addressed using the ADDR2 addressing mode. The address is fetched from Az,
; which is then post-decremented by the amount in #size. The #size is 
; automatically chosen by the CPU to be 1 since the word size accessed by 
; this instruction is 8-bit. 
ST.8 ADDR2,#0x0B            ; field
ST.8 *(Az--#size),#0x0B     ; addressing mode
ST.8 *(Az--#1),#0x0B        ; actual assembly