SPRUIY9B May   2021  – October 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Key Features
  5. 2EVM Revisions and Assembly Variants
  6. 3Important Usage Notes
  7. 4System Description
    1. 4.1 Key Features
    2. 4.2 Functional Block Diagram
    3. 4.3 Power-On/Off Procedures
      1. 4.3.1 Power-On Procedure
      2. 4.3.2 Power-Off Procedure
    4. 4.4 Peripheral and Major Component Description
      1. 4.4.1  Clocking
        1. 4.4.1.1 Ethernet PHY Clock
        2. 4.4.1.2 AM64x SoC Clock
      2. 4.4.2  Reset
      3. 4.4.3  Power
        1. 4.4.3.1 Power Input
        2. 4.4.3.2 USB Type-C Interface for Power Input
        3. 4.4.3.3 Power Fault Indication
        4. 4.4.3.4 Power Supply
        5. 4.4.3.5 Power Sequencing
        6. 4.4.3.6 Power Supply
      4. 4.4.4  Configuration
        1. 4.4.4.1 Boot Modes
      5. 4.4.5  JTAG
      6. 4.4.6  Test Automation
      7. 4.4.7  UART Interface
      8. 4.4.8  Memory Interfaces
        1. 4.4.8.1 LPDDR4 Interface
        2. 4.4.8.2 MMC Interface
          1. 4.4.8.2.1 Micro SD Interface
          2. 4.4.8.2.2 WiLink Interface
          3. 4.4.8.2.3 OSPI Interface
          4. 4.4.8.2.4 Board ID EEPROM Interface
      9. 4.4.9  Ethernet Interface
        1. 4.4.9.1 DP83867 PHY Default Configuration
        2. 4.4.9.2 DP83867 – Power, Clock, Reset, Interrupt and LEDs
        3. 4.4.9.3 Industrial Application LEDs
      10. 4.4.10 USB 3.0 Interface
      11. 4.4.11 PRU Connector
      12. 4.4.12 User Expansion Connector
      13. 4.4.13 MCU Connector
      14. 4.4.14 Interrupt
      15. 4.4.15 I2C Interface
      16. 4.4.16 IO Expander (GPIOs)
  8. 5Known Issues
    1. 5.1 Issue 1: LP8733x Max output Capacitance Spec Exceeded on LDO0 and LDO1
    2. 5.2 Issue 2: LP8733x Output Voltage of 0.9V Exceeds AM64x VDDR_CORE max Voltage Spec of 0.895 V
    3. 5.3 Issue 3 - SDIO Devices on MMC0 Require Careful Trace Lengths to Meet Interface Timing Requirements
    4. 5.4 Issue 4 - LPDDR4 Data Rate Limitation in Stressful Conditions
    5. 5.5 Issue 5 - Junk Character
    6. 5.6 Issue 6 - Test Power Down Signal Floating
    7. 5.7 Issue 7 - uSD Boot Not Working
  9. 6Regulatory Compliance
  10. 7Revision History

4.4.3.4 Power Supply

The SK-AM64B EVM board utilizes one PMIC and three discrete regulators to supply the necessary voltage and power to SOC, various memories, Wi-link module and other peripherals on the board. Probe points for power supplies provided on the SKEVM Board are mentioned in Table 4-4.

Table 4-4 Power Test Points
SI. No Power Supply Probe Point Ground Probe Point Expected Voltage (V)
Points on Top Side
1 VUSB_MAIN TP28 DGND J3.2 5
2 XDS_USB_VBUS TP75 DGND J3.2 5
3 VCC_3V3_SYS TP80 DGND J3.2 3.3
4 VDDAR_CORE TP85 DGND J3.2 0.85
5 VPP_1V8 TP89 DGND J3.2 0
6 VDD_CORE TP81 DGND J3.2 0.75
7 VDD_LPDDR4 TP83 DGND J3.2 1.1
8 VDD_1V0 TP88 DGND J3.2 1
9 VCC1V8 TP82. DGND J3.2 1.8
10 VDD_PHY_2V5 TP87 DGND J3.2 2.5
11 VDDSHV_SD_IO_PMIC TP84 DGND J3.2 3.3
12 VDD_MMC1 C47.1 DGND J3.2 3.3
13 VBUS_USB_CP2105 TP76 DGND J3.2 5
14 VCC3V3_XDS TP74 DGND J3.2 3.3
15 VDDSHV_SD_IO TP15 DGND J3.2 3.3
Points on Bottom Side
16 VCC3V3SYS_EXT TP78 DGND J3.2 3.3
17 VDDA_1V8 TP86 DGND J3.2 1.8
18 VCC3V3_TA C340.1 DGND J3.2 3.3
19 VCC3V3_TA_XDS C421.1 DGND J3.2 3.3

Table 4-5 gives details about power-good LEDs provided on SKEVM board to give users positive confirmation of the status of each supply. Figure 4-7 highlights the power-good LEDs in SK EVM board.

Table 4-5 Power LEDs
SI.No Power Supply LED Part Reference
1 VCC3V3SYS_EXT LD2
2 VCC_3V3_SYS LD16
3 VDDAR_CORE LD16
4 VDDA_1V8 LD16
5 VDD_LPDDR4 LD16
6 VDD_CORE LD16
7 VCC1V8 LD16
8 VDDSHV_SD_IO_PMIC LD16
9 VDD_PHY_2V5 LD16
10 VDDA_1V8 LD16
11 VDD_CP2105 LD18