SPRUJ40C may   2022  – may 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1EVM Revisions and Assembly Variants
  5. 2System Description
    1. 2.1 Key Features
      1. 2.1.1 Thermal Compliance
      2. 2.1.2 Processor
      3. 2.1.3 Power Supply
      4. 2.1.4 Memory
      5. 2.1.5 JTAG/Emulator
      6. 2.1.6 Supported Interfaces and Peripherals
      7. 2.1.7 Expansion Connectors/Headers to Support Application Specific Add‐On Boards
    2. 2.2 Functional Block Diagram (SK-AM62 and SK-AM62B)
    3. 2.3 Functional Block Diagram (SK-AM62-P1 and SK-AM62B-P1)
    4. 2.4 AM62x SKEVM Interface Mapping
    5. 2.5 Power ON/OFF Procedures
      1. 2.5.1 Power-On Procedure
      2. 2.5.2 Power-Off Procedure
      3. 2.5.3 Power Test Points
    6. 2.6 Peripheral and Major Component Description
      1. 2.6.1  Clocking
        1. 2.6.1.1 Peripheral Ref Clock
      2. 2.6.2  Reset
      3. 2.6.3  OLDI Display Interface
      4. 2.6.4  CSI Interface
      5. 2.6.5  Audio Codec Interface
      6. 2.6.6  HDMI Display Interface
      7. 2.6.7  JTAG Interface
      8. 2.6.8  Test Automation Header
      9. 2.6.9  UART Interface
      10. 2.6.10 USB Interface
        1. 2.6.10.1 USB 2.0 Type A Interface
        2. 2.6.10.2 USB 2.0 Type C Interface
      11. 2.6.11 Memory Interfaces
        1. 2.6.11.1 DDR4 Interface
        2. 2.6.11.2 OSPI Interface
        3. 2.6.11.3 MMC Interfaces
          1. 2.6.11.3.1 MMC0 - eMMC Interface
          2. 2.6.11.3.2 MMC1 - Micro SD Interface
          3. 2.6.11.3.3 MMC2 - Wilink Interface
        4. 2.6.11.4 EEPROM
      12. 2.6.12 Ethernet Interface
        1. 2.6.12.1 CPSW Ethernet PHY 2 Default Configuration
        2. 2.6.12.2 CPSW Ethernet PHY 1 Default Configuration
      13. 2.6.13 GPIO Port Expander
      14. 2.6.14 GPIO Mapping
      15. 2.6.15 Power
        1. 2.6.15.1 Power Requirements
        2. 2.6.15.2 Power Input
        3. 2.6.15.3 Power Supply
        4. 2.6.15.4 Power Sequencing
        5. 2.6.15.5 AM62x SoC Power
        6. 2.6.15.6 Current Monitoring
      16. 2.6.16 AM62x SKEVM User Setup/Configuration
        1. 2.6.16.1 EVM DIP Switches
        2. 2.6.16.2 Boot Modes
        3. 2.6.16.3 User Test LEDs
      17. 2.6.17 Expansion Headers
        1. 2.6.17.1 PRU Connector
        2. 2.6.17.2 User Expansion Connector
        3. 2.6.17.3 MCU Connector
      18. 2.6.18 Interrupt
      19. 2.6.19 I2C Address Mapping
  6. 3Known Issues and Modifications
    1. 3.1  Issue 1 - HDMI/DSS Incorrect Colors on E1
    2. 3.2  Issue 2 - J9 and J10 Header Alignment on E1
    3. 3.3  Issue 3 - USB Boot descoped on E1
    4. 3.4  Issue 4 - OLDI Connector Orientation and Pinout
    5. 3.5  Issue 5 - Bluetooth descoped on E2 EVMs
    6. 3.6  Issue 6 - Ethernet PHY CLK Skew Default Strapping Changes
    7. 3.7  Issue 7 - TEST_POWERDOWN changes
    8. 3.8  Issue 8 - MMC1_SDCD spurious interrupts
    9. 3.9  Issue 9 - PD Controller I2C2 IRQ Not Pinned Out
    10. 3.10 Issue 10 - INA Current Monitor Adress Changes
    11. 3.11 Issue 11 - Test Automation I2C Buffer Changes
  7.   Regulatory Compliance
  8.   Revision History

2.6.17.1 PRU Connector

AM62x SKEVM has a 20 pin PRU Header which offers Low speed connection to the PRG0 Interface.

PRU_ICSSG signals from PRG0 Port (PRG0_PRU0) are connected to a 10x2 standard 0.1” spaced Receptacle connector Mfr Part # PREC010DAAN-RC. The connector features PR0_PRU0_GPO [0: 7], SoC_I2C0, +3.3V PWR and Ground reference. INTn signal from PRU Header is wired along with the CPSW PHY interrupts and connected to the EXTINTn pin of the SoC.

The 3.3V supply is current limited to 500mA. This is achieved by using load switch TPS22902YFPR. Enable for the load switch is controlled by IO expander. Signals routed from the PRU Connector are listed in Table 2-24

GUID-052C6AC9-2E9D-4558-8E42-2185B42B04DC-low.png
Table 2-24 PRU Header (J10) Pin-out
Pin No. SoC Ball No. Net name Pin Multiplexed signal
1 - VCC3V3_PRU
2 - DGND
3 - PRU_DETECT
4 F22 PRU_RESETz RESETSTATz
5 D16 PRU_INTn EXTINTn/ GPIO1_31
6 B16 SoC_I2C0_SCL I2C0_SCL/ PR0_IEP0_EDIO_DATA_IN_OUT30/ SYNC0_OUT/ OBSCLK0/ UART1_DCDn/ EQEP2_A EHRPWM_SOCA/ GPIO1_26/ ECAP1_IN_APWM_OUT / SPI2_CS0
7 - NC
8 A16 SoC_I2C0_SDA I2C0_SDA/ PR0_IEP0_EDIO_DATA_IN_OUT31/ SPI2_CS2/ TIMER_IO5/ UART1_DSRn/ EQEP2_B/ EHRPWM_SOCB/ GPIO1_27/ ECAP2_IN_APWM_OUT
9 NC
10 - NC
11 - NC
12 - NC
13 M25 PR0_PRU0_GPO0 GPMC0_AD0/ PR0_PRU1_GPO8/ PR0_PRU1_GPI8/ MCASP2_AXR4/ PR0_PRU0_GPO0/ PR0_PRU0_GPI0/ TRC_CLK/ GPIO0_15/ DDR0_IO_PLL_TESTOUT0P/ DDR0_IO_PLL_TESTOUT1P/ GPIO1_112/ LED_DIO0
14 N23 PR0_PRU0_GPO1 GPMC0_AD1/ PR0_PRU1_GPO9/ PR0_PRU1_GPI9/ MCASP2_AXR5/ PR0_PRU0_GPO1/ PR0_PRU0_GPI1/ TRC_CTL/ GPIO0_16/ DDR0_IO_PLL_REFCLK_TEST0P/ DDR0_IO_PLL_REFCLK_TEST1P/ GPIO1_113/ LED_DIO1
15 N24 PR0_PRU0_GPO2 GPMC0_AD2/ PR0_PRU1_GPO10/ PR0_PRU1_GPI10/ MCASP2_AXR6/ PR0_PRU0_GPO2/ PR0_PRU0_GPI2/ TRC_DATA0/ GPIO0_17
16 N25 PR0_PRU0_GPO3 GPMC0_AD3/PR0_PRU1_GPO11/PR0_PRU1_GPI11/MCASP2_AXR7/PR0_PRU0_GPO3/PR0_PRU0_GPI3/TRC_DATA1/GPIO0_18
17 P24 PR0_PRU0_GPO4 GPMC0_AD4/PR0_PRU1_GPO12/PR0_PRU1_GPI12/MCASP2_AXR8/PR0_PRU0_GPO4/PR0_PRU0_GPI4/TRC_DATA2/GPIO0_19
18 P22 PR0_PRU0_GPO5 GPMC0_AD5/PR0_PRU1_GPO13/PR0_PRU1_GPI13/MCASP2_AXR9/PR0_PRU0_GPO5/PR0_PRU0_GPI5/TRC_DATA3/GPIO0_20
19 P21 PR0_PRU0_GPO6 GPMC0_AD6/PR0_PRU1_GPO14/PR0_PRU1_GPI14/MCASP2_AXR10/PR0_PRU0_GPO6/PR0_PRU0_GPI6/TRC_DATA4/GPIO0_21
20 R23 PR0_PRU0_GPO7 GPMC0_AD7/PR0_PRU1_GPO15/PR0_PRU1_GPI15/MCASP2_AXR11/PR0_PRU0_GPO7/PR0_PRU0_GPI7/TRC_DATA5/GPIO0_22