SPRUJ40C may   2022  – may 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1EVM Revisions and Assembly Variants
  5. 2System Description
    1. 2.1 Key Features
      1. 2.1.1 Thermal Compliance
      2. 2.1.2 Processor
      3. 2.1.3 Power Supply
      4. 2.1.4 Memory
      5. 2.1.5 JTAG/Emulator
      6. 2.1.6 Supported Interfaces and Peripherals
      7. 2.1.7 Expansion Connectors/Headers to Support Application Specific Add‐On Boards
    2. 2.2 Functional Block Diagram (SK-AM62 and SK-AM62B)
    3. 2.3 Functional Block Diagram (SK-AM62-P1 and SK-AM62B-P1)
    4. 2.4 AM62x SKEVM Interface Mapping
    5. 2.5 Power ON/OFF Procedures
      1. 2.5.1 Power-On Procedure
      2. 2.5.2 Power-Off Procedure
      3. 2.5.3 Power Test Points
    6. 2.6 Peripheral and Major Component Description
      1. 2.6.1  Clocking
        1. 2.6.1.1 Peripheral Ref Clock
      2. 2.6.2  Reset
      3. 2.6.3  OLDI Display Interface
      4. 2.6.4  CSI Interface
      5. 2.6.5  Audio Codec Interface
      6. 2.6.6  HDMI Display Interface
      7. 2.6.7  JTAG Interface
      8. 2.6.8  Test Automation Header
      9. 2.6.9  UART Interface
      10. 2.6.10 USB Interface
        1. 2.6.10.1 USB 2.0 Type A Interface
        2. 2.6.10.2 USB 2.0 Type C Interface
      11. 2.6.11 Memory Interfaces
        1. 2.6.11.1 DDR4 Interface
        2. 2.6.11.2 OSPI Interface
        3. 2.6.11.3 MMC Interfaces
          1. 2.6.11.3.1 MMC0 - eMMC Interface
          2. 2.6.11.3.2 MMC1 - Micro SD Interface
          3. 2.6.11.3.3 MMC2 - Wilink Interface
        4. 2.6.11.4 EEPROM
      12. 2.6.12 Ethernet Interface
        1. 2.6.12.1 CPSW Ethernet PHY 2 Default Configuration
        2. 2.6.12.2 CPSW Ethernet PHY 1 Default Configuration
      13. 2.6.13 GPIO Port Expander
      14. 2.6.14 GPIO Mapping
      15. 2.6.15 Power
        1. 2.6.15.1 Power Requirements
        2. 2.6.15.2 Power Input
        3. 2.6.15.3 Power Supply
        4. 2.6.15.4 Power Sequencing
        5. 2.6.15.5 AM62x SoC Power
        6. 2.6.15.6 Current Monitoring
      16. 2.6.16 AM62x SKEVM User Setup/Configuration
        1. 2.6.16.1 EVM DIP Switches
        2. 2.6.16.2 Boot Modes
        3. 2.6.16.3 User Test LEDs
      17. 2.6.17 Expansion Headers
        1. 2.6.17.1 PRU Connector
        2. 2.6.17.2 User Expansion Connector
        3. 2.6.17.3 MCU Connector
      18. 2.6.18 Interrupt
      19. 2.6.19 I2C Address Mapping
  6. 3Known Issues and Modifications
    1. 3.1  Issue 1 - HDMI/DSS Incorrect Colors on E1
    2. 3.2  Issue 2 - J9 and J10 Header Alignment on E1
    3. 3.3  Issue 3 - USB Boot descoped on E1
    4. 3.4  Issue 4 - OLDI Connector Orientation and Pinout
    5. 3.5  Issue 5 - Bluetooth descoped on E2 EVMs
    6. 3.6  Issue 6 - Ethernet PHY CLK Skew Default Strapping Changes
    7. 3.7  Issue 7 - TEST_POWERDOWN changes
    8. 3.8  Issue 8 - MMC1_SDCD spurious interrupts
    9. 3.9  Issue 9 - PD Controller I2C2 IRQ Not Pinned Out
    10. 3.10 Issue 10 - INA Current Monitor Adress Changes
    11. 3.11 Issue 11 - Test Automation I2C Buffer Changes
  7.   Regulatory Compliance
  8.   Revision History

2.6.10.1 USB 2.0 Type A Interface

The USB 2.0 HOST Interface is offered through a USB Type-A Port on the USB1 controller on the AM62x SoC.

The USB Signals are connected on E1 to a USB 2.0 HUB Mfr Part# TUSB4020BI to provide two USB 2.0 Host ports. TUSB4020BI is a two port USB 2.0 HUB, which provides USB high-speed/full-speed connections on the upstream port and provides USB high-speed, full-speed, or low-speed connections on the downstream ports. On-chip 24 MHz crystal is used to provide clock to the USB HUB. USB0_DRVVBUS from SoC is connected to USB_VBUS pin of the HUB through resistor divider network to limit the voltage level below 1.155 V. The Reset to the HUB is given by SoC RESETSTATz output.

The GANGED/SMBA2/HS_UP pin and FULLPWRMGMTz/ SMBA1 pin of USB HUB are pulled down to enable individual power control of the ports when power switching is enabled. The PWRCTL_POL pin of USB HUB is pulled down to make PWRCTL polarity active high. The PWRCTL1/BATEN1 pin and PWRCTL2/BATEN2 pin of HUB is connected to enable pins of Current limit switches for VBUS supply control on downstream ports. The USB2.0 ports shall provide maximum of 500 mA, 5 V to the devices as per USB2.0 specifications. The USB HUB strapping options are provided as follows.

On E2 and future revisions, the USB Hub has been dropped in favor of connecting the onboard USB Controller directly to a single Type-A connector.

Note: Please see Section 3.3 for details on the differences between SK-AM62 E1 and latter implementation of the USB Subsystem.

GUID-04E0284A-104F-48F8-AD30-ADD24BB8B122-low.png

USB Data lines from Type-A connectors are connected to the Current Limit Load Switch and ESD Protection IC Mfr Part# TPD3S014DBVR. This switch limits the current to 500mA and dissipates the ESD strikes above the maximum level specified in the IEC 61000-4-2.

The USB HUB is powered by 3.3V from board IO supply and the 1.1V supply from Dedicated LDO Mfr Part# TLV75511PDQNR.

GUID-B1F2AFFB-FCD1-4F76-A9C7-7A9830CF45D2-low.png