SPRUJ40C may   2022  – may 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1EVM Revisions and Assembly Variants
  5. 2System Description
    1. 2.1 Key Features
      1. 2.1.1 Thermal Compliance
      2. 2.1.2 Processor
      3. 2.1.3 Power Supply
      4. 2.1.4 Memory
      5. 2.1.5 JTAG/Emulator
      6. 2.1.6 Supported Interfaces and Peripherals
      7. 2.1.7 Expansion Connectors/Headers to Support Application Specific Add‐On Boards
    2. 2.2 Functional Block Diagram (SK-AM62 and SK-AM62B)
    3. 2.3 Functional Block Diagram (SK-AM62-P1 and SK-AM62B-P1)
    4. 2.4 AM62x SKEVM Interface Mapping
    5. 2.5 Power ON/OFF Procedures
      1. 2.5.1 Power-On Procedure
      2. 2.5.2 Power-Off Procedure
      3. 2.5.3 Power Test Points
    6. 2.6 Peripheral and Major Component Description
      1. 2.6.1  Clocking
        1. 2.6.1.1 Peripheral Ref Clock
      2. 2.6.2  Reset
      3. 2.6.3  OLDI Display Interface
      4. 2.6.4  CSI Interface
      5. 2.6.5  Audio Codec Interface
      6. 2.6.6  HDMI Display Interface
      7. 2.6.7  JTAG Interface
      8. 2.6.8  Test Automation Header
      9. 2.6.9  UART Interface
      10. 2.6.10 USB Interface
        1. 2.6.10.1 USB 2.0 Type A Interface
        2. 2.6.10.2 USB 2.0 Type C Interface
      11. 2.6.11 Memory Interfaces
        1. 2.6.11.1 DDR4 Interface
        2. 2.6.11.2 OSPI Interface
        3. 2.6.11.3 MMC Interfaces
          1. 2.6.11.3.1 MMC0 - eMMC Interface
          2. 2.6.11.3.2 MMC1 - Micro SD Interface
          3. 2.6.11.3.3 MMC2 - Wilink Interface
        4. 2.6.11.4 EEPROM
      12. 2.6.12 Ethernet Interface
        1. 2.6.12.1 CPSW Ethernet PHY 2 Default Configuration
        2. 2.6.12.2 CPSW Ethernet PHY 1 Default Configuration
      13. 2.6.13 GPIO Port Expander
      14. 2.6.14 GPIO Mapping
      15. 2.6.15 Power
        1. 2.6.15.1 Power Requirements
        2. 2.6.15.2 Power Input
        3. 2.6.15.3 Power Supply
        4. 2.6.15.4 Power Sequencing
        5. 2.6.15.5 AM62x SoC Power
        6. 2.6.15.6 Current Monitoring
      16. 2.6.16 AM62x SKEVM User Setup/Configuration
        1. 2.6.16.1 EVM DIP Switches
        2. 2.6.16.2 Boot Modes
        3. 2.6.16.3 User Test LEDs
      17. 2.6.17 Expansion Headers
        1. 2.6.17.1 PRU Connector
        2. 2.6.17.2 User Expansion Connector
        3. 2.6.17.3 MCU Connector
      18. 2.6.18 Interrupt
      19. 2.6.19 I2C Address Mapping
  6. 3Known Issues and Modifications
    1. 3.1  Issue 1 - HDMI/DSS Incorrect Colors on E1
    2. 3.2  Issue 2 - J9 and J10 Header Alignment on E1
    3. 3.3  Issue 3 - USB Boot descoped on E1
    4. 3.4  Issue 4 - OLDI Connector Orientation and Pinout
    5. 3.5  Issue 5 - Bluetooth descoped on E2 EVMs
    6. 3.6  Issue 6 - Ethernet PHY CLK Skew Default Strapping Changes
    7. 3.7  Issue 7 - TEST_POWERDOWN changes
    8. 3.8  Issue 8 - MMC1_SDCD spurious interrupts
    9. 3.9  Issue 9 - PD Controller I2C2 IRQ Not Pinned Out
    10. 3.10 Issue 10 - INA Current Monitor Adress Changes
    11. 3.11 Issue 11 - Test Automation I2C Buffer Changes
  7.   Regulatory Compliance
  8.   Revision History

2.6.14 GPIO Mapping

The Table 2-11 describes the detailed GPIO mapping of AM62x SoC with AM62x SKEVM peripherals.

Table 2-11 GPIO Mapping
Sl.No GPIO Description GPIO NETNAME Functionality GPIO Used SoC Muxed Signal Name Direction With Respect to Control Default State Active State Voltage on SoC Side Voltage on SK-EVM
1 Enable for WLAN Interface WLAN_EN ENABLE GPIO0_71 MMC2_SDCD OUTPUT LOW HIGH VDDSHV6 SoC_DVDD1V8
2 WLAN Interrupt WLAN_IRQ INTERRUPT GPIO0_72 MMC2_SDWP INPUT HIGH LOW VDDSHV6 SoC_DVDD1V8
3 Enable for BT Interface BT_EN_SOC ENABLE MCU_GPIO0_1 MCU_SPIO_CS0 OUTPUT LOW HIGH VDDSHV_MCU SoC_DVDD3V3
4 CPSW Ethernet PHY Interrupt CPSW_RGMII_INTn/PRu_INTn INTERRUPT GPIO1_31 EXTINTn INPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
PRU Connector Interrupt
5 OSPI Reset Control GPIO GPIO_OSPI_RSTn RESET GPIO0_12 OSPI0_CSn1 OUTPUT HIGH LOW VDDSHV1 SoC_DVDD1V8
6 OSPI Interrupt OSPI_INTn INTERRUPT GPIO0_13 OSPI0_CSn2 INPUT HIGH LOW VDDSHV1 SoC_DVDD1V8
7 SD Card IO Voltage Select VSEL_SD ENABLE GPIO0_31 GPMC0_CLK OUTPUT LOW HIGH VDDSHV3 SoC_DVDD3V3
8 IO Expander Interrupt MCU_GPIO0_15 INTERRUPT MCU_GPIO0_15 MCU_MCAN1_TX INPUT HIGH LOW VDDSHV_CANUART SoC_DVDD3V3
9 TEST GPIO1 from Test Automation Connector/User Interrupt
10 USER Test LED 1 SOC_GPIO_49 GPIO GPIO1_49 MMC1_SDWP OUTPUT LOW HIGH VDDSHV0 SoC_DVDD3V3
IO EXPANDER - 01
1 eMMC Reset control GPIO GPIO_eMMC_RSTn RESET IO EXPANDER - P00 OUTPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
2 CPSW Ethernet PHY-1 Reset control GPIO GPIO_CPSW1_RST RESET IO EXPANDER - P01 OUTPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
3 CPSW Ethernet PHY-2 Reset control GPIO GPIO_CPSW2_RST RESET IO EXPANDER - P02 OUTPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
4 SD Card Load Switch Enable MMC1_SD_EN ENABLE IO EXPANDER - P03 OUTPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
5 SOC eFUSE Voltage(VPP=1.8V) Regulator Enable VPP_LDO_EN ENABLE IO EXPANDER - P04 OUTPUT LOW HIGH VDDSHV0 SoC_DVDD3V3
6 EXP CONN 3.3V Power Switch Enable RPI_PS_3V3_EN ENABLE IO EXPANDER - P05 OUTPUT LOW HIGH VDDSHV0 SoC_DVDD3V3
7 EXP CONN 5V Power Switch Enable RPI_PS_5V0_EN ENABLE IO EXPANDER - P06 OUTPUT LOW HIGH VDDSHV0 SoC_DVDD3V3
8 Audio Codec Reset Control GPIO GPIO_AUD_RSTn RESET IO EXPANDER - P07 OUTPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
9 EXP CONN HAT Board Detection RPI_HAT_DETECT DETECTION IO EXPANDER - P010 INPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
10 PRU Board Detection PRU_DETECT DETECTION IO EXPANDER - P11 INPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
11 SOC UART1 MUX Select UART1_MUX_SEL SELECT IO EXPANDER - P12 OUTPUT LOW HIGH VDDSHV0 SoC_DVDD3V3
12 Enable for Wilink Level Translators WL_LT_EN ENABLE IO EXPANDER - P13 OUTPUT LOW HIGH VDDSHV0 SoC_DVDD3V3
13 HDMI Transmitter Reset Control GPIO GPIO_HDMI_RSTn RESET IO EXPANDER - P14 OUTPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
14 Rasberry Pi Cameraa CSI0 GPIO1 CSI_GPIO1 INPUT/OUTPUT IO EXPANDER - P15 NA NA NA VDDSHV0 SoC_DVDD3V3
15 Rasberry Pi Cameraa CSI0 GPIO2 CSI_GPIO2 INPUT/OUTPUT IO EXPANDER - P16 NA NA NA VDDSHV0 SoC_DVDD3V3
16 PRU Power Switch Enable PRU_3V3_EN ENABLE IO EXPANDER - P17 OUTPUT LOW HIGH VDDSHV0 SoC_DVDD3V3
17 HDMI Interrupt HDMI_INTn INTERRUPT IO EXPANDER - P20 INPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
18 TEST GPIO2 from Test Automation Connector TEST_GPIO2 GPIO for Communications with AM62X IO EXPANDER - P21 INPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
19 MCASP2 Enable and Direction Control AUD_BUF_EN ENABLE IO EXPANDER - P22 OUTPUT LOW HIGH VDDSHV0 SoC_DVDD3V3
20 WL_BUF_EN ENABLE IO EXPANDER - P23 OUTPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
21 AUD_BUF_CLK_DIR DIRECTION CONTROL IO EXPANDER - P24 OUTPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
22 WL_BUF_CLK_DIR DIRECTION CONTROL IO EXPANDER - P25 OUTPUT HIGH LOW VDDSHV0 SoC_DVDD3V3
23 OLDI Display Backlight Enable VLED_ENB ENABLE IO EXPANDER - P26 OUTPUT LOW HIGH VDDSHV0 SoC_DVDD3V3
24 User Test LED 2 IO_EXP_TEST_LED GPIO IO EXPANDER - P27 OUTPUT LOW HIGH VDDSHV0 SoC_DVDD3V3