SPRUJD3A July   2025  – October 2025 F28E120SB , F28E120SC

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit (FPU)
  5. 3 System Control and Interrupts
    1. 3.1  Introduction
      1. 3.1.1 SYSCTL Related Collateral
      2. 3.1.2 LOCK Protection on System Configuration Registers
      3. 3.1.3 EALLOW Protection
    2. 3.2  Power Management
    3. 3.3  Device Identification and Configuration Registers
    4. 3.4  Resets
      1. 3.4.1  Reset Sources
      2. 3.4.2  External Reset (XRS)
      3. 3.4.3  Power-On Reset (POR)
      4. 3.4.4  Brown-Out-Reset (BOR)
      5. 3.4.5  Watchdog Reset (WDRS)
      6. 3.4.6  NMI Watchdog Reset (NMIWDRS)
      7. 3.4.7  Debugger Reset (SYSRS)
      8. 3.4.8  DCSM Safe Code Copy Reset (SCCRESET)
      9. 3.4.9  Simulate External Reset (SIMRESET.XRS)
      10. 3.4.10 Simulate CPU Reset (SIMRESET_CPU1RS)
    5. 3.5  Peripheral Interrupts
      1. 3.5.1 Interrupt Concepts
      2. 3.5.2 Interrupt Architecture
        1. 3.5.2.1 Peripheral Stage
        2. 3.5.2.2 PIE Stage
        3. 3.5.2.3 CPU Stage
      3. 3.5.3 Interrupt Entry Sequence
      4. 3.5.4 Configuring and Using Interrupts
        1. 3.5.4.1 Enabling Interrupts
        2. 3.5.4.2 Handling Interrupts
        3. 3.5.4.3 Disabling Interrupts
        4. 3.5.4.4 Nesting Interrupts
        5. 3.5.4.5 Vector Address Validity Check
      5. 3.5.5 PIE Channel Mapping
      6. 3.5.6 PIE Interrupt Priority
        1. 3.5.6.1 Channel Priority
        2. 3.5.6.2 Group Priority
      7. 3.5.7 System Error
      8. 3.5.8 Vector Tables
    6. 3.6  Exceptions and Non-Maskable Interrupts
      1. 3.6.1 Configuring and Using NMIs
      2. 3.6.2 Emulation Considerations
      3. 3.6.3 NMI Sources
        1. 3.6.3.1 Missing Clock Detection Logic
        2. 3.6.3.2 Flash Uncorrectable ECC Error
        3. 3.6.3.3 Software-Forced Error
      4. 3.6.4 Illegal Instruction Trap (ITRAP)
      5. 3.6.5 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1  Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (SYSOSC)
        2. 3.7.1.2 Backup Wide-Range Oscillator (WROSC)
        3. 3.7.1.3 External Oscillator (XTAL)
      2. 3.7.2  Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.7.3  Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4  XCLKOUT
      5. 3.7.5  Clock Connectivity
      6. 3.7.6  Clock Source and PLL Setup
      7. 3.7.7  Using an External Crystal or Resonator
      8. 3.7.8  Using an External Oscillator
      9. 3.7.9  Choosing PLL Settings
      10. 3.7.10 System Clock Setup
      11. 3.7.11 SYS PLL Bypass
      12. 3.7.12 Clock (OSCCLK) Failure Detection
        1. 3.7.12.1 Missing Clock Detection
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timer
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low Power-Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 Clock-Gating Low-Power Modes
      2. 3.10.2 IDLE
      3. 3.10.3 STANDBY
      4. 3.10.4 HALT
    11. 3.11 Memory Controller Module
      1. 3.11.1 Dedicated RAM (Mx RAM)
      2. 3.11.2 Global Shared RAM (GSx RAM)
      3. 3.11.3 Access Arbitration
      4. 3.11.4 Memory Error Detection, Correction, and Error Handling
        1. 3.11.4.1 Error Detection and Correction
        2. 3.11.4.2 Error Handling
      5. 3.11.5 Application Test Hooks for Error Detection and Correction
      6. 3.11.6 RAM Initialization
    12. 3.12 JTAG
      1. 3.12.1 JTAG Noise and TAP_STATUS
    13. 3.13 System Control Register Configuration Restrictions
    14. 3.14 Software
      1. 3.14.1 SYSCTL Examples
        1. 3.14.1.1 Missing clock detection (MCD)
        2. 3.14.1.2 XCLKOUT (External Clock Output) Configuration
    15. 3.15 SYSCTRL Registers
      1. 3.15.1  SYSCTRL Base Address Table
      2. 3.15.2  CPUTIMER_REGS Registers
      3. 3.15.3  PIE_CTRL_REGS Registers
      4. 3.15.4  WD_REGS Registers
      5. 3.15.5  NMI_INTRUPT_REGS Registers
      6. 3.15.6  XINT_REGS Registers
      7. 3.15.7  SYNC_SOC_REGS Registers
      8. 3.15.8  DMA_CLA_SRC_SEL_REGS Registers
      9. 3.15.9  DEV_CFG_REGS Registers
      10. 3.15.10 CLK_CFG_REGS Registers
      11. 3.15.11 CPU_SYS_REGS Registers
      12. 3.15.12 SYS_STATUS_REGS Registers
      13. 3.15.13 MEM_CFG_REGS Registers
      14. 3.15.14 MEMORY_ERROR_REGS Registers
      15. 3.15.15 ROM_WAIT_STATE_REGS Registers
      16. 3.15.16 TEST_ERROR_REGS Registers
      17. 3.15.17 UID_REGS Registers
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Boot Flow
      2. 4.5.2 Emulation Boot Flow
      3. 4.5.3 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 GPREG2 Usage and Configuration
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Secure Flash Boot
        1. 4.7.4.1 Secure Flash CPU1 Linker File Example
      5. 4.7.5  Memory Maps
        1. 4.7.5.1 Boot ROM Memory Maps
        2. 4.7.5.2 Reserved RAM Memory Maps
      6. 4.7.6  ROM Tables
      7. 4.7.7  Boot Modes and Loaders
        1. 4.7.7.1 Boot Modes
          1. 4.7.7.1.1 Flash Boot
          2. 4.7.7.1.2 RAM Boot
          3. 4.7.7.1.3 Wait Boot
        2. 4.7.7.2 Bootloaders
          1. 4.7.7.2.1 SCI Boot Mode
          2. 4.7.7.2.2 SPI Boot Mode
          3. 4.7.7.2.3 I2C Boot Mode
          4. 4.7.7.2.4 Parallel Boot Mode
      8. 4.7.8  GPIO Assignments
      9. 4.7.9  Secure ROM Function APIs
      10. 4.7.10 Clock Initializations
      11. 4.7.11 Boot Status Information
        1. 4.7.11.1 Booting Status
      12. 4.7.12 ROM Version
    8. 4.8 Application Notes for Using the Bootloaders
      1. 4.8.1 Bootloader Data Stream Structure
        1. 4.8.1.1 Data Stream Structure 8-bit
      2. 4.8.2 The C2000 Hex Utility
        1. 4.8.2.1 HEX2000.exe Command Syntax
    9. 4.9 Software
      1. 4.9.1 BOOT Examples
  7. 5 Dual Code Security Module (DCSM)
    1. 5.1 Introduction
      1. 5.1.1 DCSM Related Collateral
    2. 5.2 Functional Description
      1. 5.2.1 CSM Passwords
      2. 5.2.2 Emulation Code Security Logic (ECSL)
      3. 5.2.3 CPU Secure Logic
      4. 5.2.4 Execute-Only Protection
      5. 5.2.5 Password Lock
      6. 5.2.6 JTAGLOCK
      7. 5.2.7 Link Pointer and Zone Select
      8. 5.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 5.3 Flash and OTP Erase/Program
    4. 5.4 Secure Copy Code
    5. 5.5 SecureCRC
    6. 5.6 CSM Impact on Other On-Chip Resources
      1. 5.6.1 RAMOPEN
    7. 5.7 Incorporating Code Security in User Applications
      1. 5.7.1 Environments That Require Security Unlocking
      2. 5.7.2 CSM Password Match Flow
      3. 5.7.3 C Code Example to Unsecure C28x Zone1
      4. 5.7.4 C Code Example to Resecure C28x Zone1
      5. 5.7.5 Environments That Require ECSL Unlocking
      6. 5.7.6 ECSL Password Match Flow
      7. 5.7.7 ECSL Disable Considerations for any Zone
        1. 5.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 5.7.8 Device Unique ID
    8. 5.8 Software
      1. 5.8.1 DCSM Examples
        1. 5.8.1.1 Empty DCSM Tool Example
    9. 5.9 DCSM Registers
      1. 5.9.1 DCSM Base Address Table
      2. 5.9.2 DCSM_Z1_REGS Registers
      3. 5.9.3 DCSM_Z2_REGS Registers
      4. 5.9.4 DCSM_COMMON_REGS Registers
      5. 5.9.5 DCSM_Z1_OTP Registers
      6. 5.9.6 DCSM_Z2_OTP Registers
  8. 6 Flash Module
    1. 6.1  Introduction to Flash and OTP Memory
      1. 6.1.1 FLASH Related Collateral
      2. 6.1.2 Features
      3. 6.1.3 Flash Tools
      4. 6.1.4 Default Flash Configuration
    2. 6.2  Flash Bank, OTP, and Pump
    3. 6.3  Flash Wrapper
    4. 6.4  Flash and OTP Memory Performance
    5. 6.5  Flash Read Interface
      1. 6.5.1 C28x-Flash Read Interface
        1. 6.5.1.1 Standard Read Mode
        2. 6.5.1.2 Prefetch Mode
        3. 6.5.1.3 Data Cache
        4. 6.5.1.4 Flash Read Operation
    6. 6.6  Flash Erase and Program
      1. 6.6.1 Erase
      2. 6.6.2 Program
      3. 6.6.3 Verify
    7. 6.7  Error Correction Code (ECC) Protection
      1. 6.7.1 Single-Bit Data Error
      2. 6.7.2 Uncorrectable Error
      3. 6.7.3 ECC Logic Self Test
    8. 6.8  Reserved Locations Within Flash and OTP
    9. 6.9  Migrating an Application from RAM to Flash
    10. 6.10 Procedure to Change the Flash Control Registers
    11. 6.11 Software
      1. 6.11.1 FLASH Examples
        1. 6.11.1.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
    12. 6.12 FLASH Registers
      1. 6.12.1 FLASH Base Address Table
      2. 6.12.2 FLASH_CTRL_REGS Registers
      3. 6.12.3 FLASH_ECC_REGS Registers
  9. 7 Dual-Clock Comparator (DCC)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 Block Diagram
    2. 7.2 Module Operation
      1. 7.2.1 Configuring DCC Counters
      2. 7.2.2 Single-Shot Measurement Mode
      3. 7.2.3 Continuous Monitoring Mode
      4. 7.2.4 Error Conditions
    3. 7.3 Interrupts
    4. 7.4 Software
      1. 7.4.1 DCC Examples
        1. 7.4.1.1 DCC Single shot Clock verification
        2. 7.4.1.2 DCC Single shot Clock measurement
        3. 7.4.1.3 DCC Continuous clock monitoring
        4. 7.4.1.4 DCC Continuous clock monitoring
        5. 7.4.1.5 DCC Detection of clock failure
    5. 7.5 DCC Registers
      1. 7.5.1 DCC Base Address Table
      2. 7.5.2 DCC_REGS Registers
  10. 8 General-Purpose Input/Output (GPIO)
    1. 8.1  Introduction
      1. 8.1.1 GPIO Related Collateral
    2. 8.2  Configuration Overview
    3. 8.3  Digital Inputs on ADC Pins (AIOs)
    4. 8.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 8.5  Digital General-Purpose I/O Control
    6. 8.6  Input Qualification
      1. 8.6.1 No Synchronization (Asynchronous Input)
      2. 8.6.2 Synchronization to SYSCLKOUT Only
      3. 8.6.3 Qualification Using a Sampling Window
    7. 8.7  GPIO and Peripheral Muxing
      1. 8.7.1 GPIO Muxing
      2. 8.7.2 Peripheral Muxing
    8. 8.8  Internal Pullup Configuration Requirements
    9. 8.9  Open-Drain Configuration Requirements
    10. 8.10 Software
      1. 8.10.1 GPIO Examples
        1. 8.10.1.1 Device GPIO Setup
        2. 8.10.1.2 Device GPIO Toggle
        3. 8.10.1.3 Device GPIO Interrupt
        4. 8.10.1.4 External Interrupt (XINT)
      2. 8.10.2 LED Examples
    11. 8.11 GPIO Registers
      1. 8.11.1 GPIO Base Address Table
      2. 8.11.2 GPIO_CTRL_REGS Registers
      3. 8.11.3 GPIO_DATA_REGS Registers
      4. 8.11.4 GPIO_DATA_READ_REGS Registers
  11. 9 Crossbar (X-BAR)
    1. 9.1 Input X-BAR
    2. 9.2 MCPWM and GPIO Output X-BAR
      1. 9.2.1 MCPWM X-BAR
        1. 9.2.1.1 MCPWM X-BAR Architecture
      2. 9.2.2 GPIO Output X-BAR
        1. 9.2.2.1 GPIO Output X-BAR Architecture
      3. 9.2.3 X-BAR Flags
    3. 9.3 XBAR Registers
      1. 9.3.1 XBAR Base Address Table
      2. 9.3.2 INPUT_XBAR_REGS Registers
      3. 9.3.3 XBAR_REGS Registers
      4. 9.3.4 PWM_XBAR_REGS Registers
      5. 9.3.5 OUTPUT_XBAR_REGS Registers
  12. 10Direct Memory Access (DMA)
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Architecture
      1. 10.2.1 Peripheral Interrupt Event Trigger Sources
      2. 10.2.2 DMA Bus
    3. 10.3 Address Pointer and Transfer Control
    4. 10.4 Pipeline Timing and Throughput
    5. 10.5 Channel Priority
      1. 10.5.1 Round-Robin Mode
      2. 10.5.2 Channel 1 High-Priority Mode
    6. 10.6 Overrun Detection Feature
    7. 10.7 Software
      1. 10.7.1 DMA Examples
        1. 10.7.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 10.7.1.2 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    8. 10.8 DMA Registers
      1. 10.8.1 DMA Base Address Table
      2. 10.8.2 DMA_REGS Registers
      3. 10.8.3 DMA_CH_REGS Registers
  13. 11Analog Subsystem
    1. 11.1 Introduction
      1. 11.1.1 Features
      2. 11.1.2 Block Diagram
    2. 11.2 Digital Inputs on ADC Pins (AIOs)
    3. 11.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    4. 11.4 Analog Pins and Internal Connections
    5. 11.5 ASBSYS Registers
      1. 11.5.1 ASBSYS Base Address Table
      2. 11.5.2 ANALOG_SUBSYS_REGS Registers
  14. 12Analog-to-Digital Converter (ADC)
    1. 12.1  Introduction
      1. 12.1.1 Features
      2. 12.1.2 ADC Related Collateral
      3. 12.1.3 Block Diagram
    2. 12.2  ADC Configurability
      1. 12.2.1 ADC Clock Configuration
      2. 12.2.2 Resolution
      3. 12.2.3 Voltage Reference
        1. 12.2.3.1 External Reference Mode
        2. 12.2.3.2 Internal Reference Mode
        3. 12.2.3.3 Selecting Reference Mode
      4. 12.2.4 Signal Mode
        1. 12.2.4.1 Expected Conversion Results
        2. 12.2.4.2 Interpreting Conversion Results
    3. 12.3  SOC Principle of Operation
      1. 12.3.1 SOC Configuration
      2. 12.3.2 Trigger Operation
        1. 12.3.2.1 Trigger Repeaters
          1. 12.3.2.1.1 Oversampling Mode
          2. 12.3.2.1.2 Re-trigger Spread
          3. 12.3.2.1.3 Trigger Repeater Configuration
            1. 12.3.2.1.3.1 Register Shadow Updates
          4. 12.3.2.1.4 Re-Trigger Logic
          5. 12.3.2.1.5 Multi-Path Triggering Behavior
      3. 12.3.3 ADC Acquisition (Sample and Hold) Window
      4. 12.3.4 Sample Capacitor Reset
      5. 12.3.5 ADC Input Models
      6. 12.3.6 Channel Selection
    4. 12.4  SOC Configuration Examples
      1. 12.4.1 Single Conversion from MCPWM Trigger
      2. 12.4.2 Multiple Conversions from CPU Timer Trigger
      3. 12.4.3 Software Triggering of SOCs
    5. 12.5  ADC Conversion Priority
    6. 12.6  EOC and Interrupt Operation
      1. 12.6.1 Interrupt Overflow
      2. 12.6.2 Continue to Interrupt Mode
      3. 12.6.3 Early Interrupt Configuration Mode
    7. 12.7  Post-Processing Blocks
      1. 12.7.1 PPB Offset Correction
      2. 12.7.2 PPB Error Calculation
      3. 12.7.3 PPB Limit Detection and Zero-Crossing Detection
    8. 12.8  Opens/Shorts Detection Circuit (OSDETECT)
      1. 12.8.1 Open Short Detection Implementation
      2. 12.8.2 Detecting an Open Input Pin
      3. 12.8.3 Detecting a Shorted Input Pin
    9. 12.9  Power-Up Sequence
    10. 12.10 ADC Calibration
      1. 12.10.1 ADC Zero Offset Calibration
    11. 12.11 ADC Timings
      1. 12.11.1 ADC Timing Diagrams
      2. 12.11.2 Post-Processing Block Timings
    12. 12.12 Additional Information
      1. 12.12.1 Choosing an Acquisition Window Duration
      2. 12.12.2 Result Register Mapping
      3. 12.12.3 Internal Temperature Sensor
      4. 12.12.4 Designing an External Reference Circuit
      5. 12.12.5 ADC-DAC Loopback Testing
      6. 12.12.6 Internal Test Mode
    13. 12.13 Software
      1. 12.13.1 ADC Examples
        1. 12.13.1.1 ADC Software Triggering
        2. 12.13.1.2 ADC MCPWM Triggering
        3. 12.13.1.3 ADC Temperature Sensor Conversion
        4. 12.13.1.4 ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
        5. 12.13.1.5 ADC PPB Offset (adc_ppb_offset)
        6. 12.13.1.6 ADC PPB Limits (adc_ppb_limits)
        7. 12.13.1.7 ADC SOC Oversampling
        8. 12.13.1.8 ADC Trigger Repeater Oversampling
    14. 12.14 ADC Registers
      1. 12.14.1 ADC Base Address Table
      2. 12.14.2 ADC_LITE_RESULT_REGS Registers
      3. 12.14.3 ADC_LITE_REGS Registers
  15. 13Comparator Subsystem (CMPSS)
    1. 13.1 Introduction
      1. 13.1.1 Features
      2. 13.1.2 CMPSS Related Collateral
      3. 13.1.3 Block Diagram
    2. 13.2 Comparator
    3. 13.3 Reference DAC
    4. 13.4 Digital Filter
      1. 13.4.1 Filter Initialization Sequence
    5. 13.5 Using the CMPSS
      1. 13.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 13.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 13.5.3 Calibrating the CMPSS
      4. 13.5.4 Enabling and Disabling the CMPSS Clock
    6. 13.6 CMPSS DAC Output
    7. 13.7 Software
      1. 13.7.1 CMPSS Examples
      2. 13.7.2 CMPSS_LITE Examples
        1. 13.7.2.1 CMPSSLITE Asynchronous Trip
    8. 13.8 CMPSS Registers
      1. 13.8.1 CMPSS Base Address Table
      2. 13.8.2 CMPSS_LITE_REGS Registers
  16. 14Programmable Gain Amplifier (PGA)
    1. 14.1  Programmable Gain Amplifier (PGA) Overview
      1. 14.1.1 Features
      2. 14.1.2 Block Diagram
    2. 14.2  Linear Output Range
    3. 14.3  Gain Values
    4. 14.4  Modes of Operation
      1. 14.4.1 Buffer Mode
      2. 14.4.2 Standalone Mode
      3. 14.4.3 Non-inverting Mode
      4. 14.4.4 Subtractor Mode
    5. 14.5  External Filtering
      1. 14.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 14.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 14.6  Error Calibration
      1. 14.6.1 Offset Error
      2. 14.6.2 Gain Error
    7. 14.7  Chopping Feature
    8. 14.8  Enabling and Disabling the PGA Clock
    9. 14.9  Lock Register
    10. 14.10 Analog Front-End Integration
      1. 14.10.1 Analog-to-Digital Converter (ADC)
        1. 14.10.1.1 Unfiltered Acquisition Window
        2. 14.10.1.2 Filtered Acquisition Window
      2. 14.10.2 Comparator Subsystem (CMPSS)
      3. 14.10.3 Alternate Functions
    11. 14.11 Examples
      1. 14.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 14.11.2 Buffer Mode
      3. 14.11.3 Low-Side Current Sensing
      4. 14.11.4 Bidirectional Current Sensing
    12. 14.12 Software
      1. 14.12.1 PGA Examples
        1. 14.12.1.1 PGA CMPSSDAC-ADC External Loopback Example
    13. 14.13 PGA Registers
      1. 14.13.1 PGA Base Address Table
      2. 14.13.2 PGA_REGS Registers
  17. 15Multi-Channel Pulse Width Modulator (MCPWM)
    1. 15.1  Introduction
      1. 15.1.1 PWM Related Collateral
      2. 15.1.2 Submodule Overview
    2. 15.2  Configuring Device Pins
    3. 15.3  MCPWM Modules Overview
    4. 15.4  Time-Base (TB) Submodule
      1. 15.4.1 Purpose of the Time-Base Submodule
      2. 15.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 15.4.3 Calculating PWM Period and Frequency
        1. 15.4.3.1 Time-Base Period Shadow Register
        2. 15.4.3.2 Time-Base Clock Synchronization
        3. 15.4.3.3 Time-Base Counter Synchronization
        4. 15.4.3.4 MCPWM SYNC Selection
      4. 15.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 15.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 15.4.6 Global Load
        1. 15.4.6.1 One-Shot Load Mode
    5. 15.5  Counter-Compare (CC) Submodule
      1. 15.5.1 Purpose of the Counter-Compare Submodule
      2. 15.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 15.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 15.5.4 Count Mode Timing Waveforms
    6. 15.6  Action-Qualifier (AQ) Submodule
      1. 15.6.1 Purpose of the Action-Qualifier Submodule
      2. 15.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 15.6.3 Action-Qualifier Event Priority
      4. 15.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 15.6.5 Configuration Requirements for Common Waveforms
    7. 15.7  Dead-Band Generator (DB) Submodule
      1. 15.7.1 Purpose of the Dead-Band Submodule
      2. 15.7.2 Dead-Band Submodule Additional Operating Modes
      3. 15.7.3 Operational Highlights for the Dead-Band Submodule
    8. 15.8  Trip-Zone (TZ) Submodule
      1. 15.8.1 Purpose of the Trip-Zone Submodule
      2. 15.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 15.8.2.1 Trip-Zone Configurations
      3. 15.8.3 Generating Trip Event Interrupts
    9. 15.9  Event-Trigger (ET) Submodule
      1. 15.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 15.10 PWM Crossbar (X-BAR)
    11. 15.11 Software
      1. 15.11.1 MCPWM Examples
        1. 15.11.1.1 MCPWM Basic PWM Generation and Updates
        2. 15.11.1.2 MCPWM Basic PWM Generation and Updates
        3. 15.11.1.3 MCPWM Basic PWM generation With DeadBand
        4. 15.11.1.4 MCPWM Basic PWM Generation and Updates without Sysconfig
        5. 15.11.1.5 MCPWM PWM Tripzone Feature Showcase
        6. 15.11.1.6 MCPWM Global Load Feature Showcase
        7. 15.11.1.7 MCPWM DMA Configuration for Dynamic PWM Control
    12. 15.12 MCPWM Registers
      1. 15.12.1 MCPWM Base Address Table
      2. 15.12.2 MCPWM_6CH_REGS Registers
      3. 15.12.3 MCPWM_2CH_REGS Registers
  18. 16Enhanced Capture (eCAP)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 ECAP Related Collateral
    2. 16.2 Description
    3. 16.3 Configuring Device Pins for the eCAP
    4. 16.4 Capture and APWM Operating Mode
    5. 16.5 Capture Mode Description
      1. 16.5.1 Event Prescaler
      2. 16.5.2 Edge Polarity Select and Qualifier
      3. 16.5.3 Continuous/One-Shot Control
      4. 16.5.4 32-Bit Counter and Phase Control
      5. 16.5.5 CAP1-CAP4 Registers
      6. 16.5.6 eCAP Synchronization
        1. 16.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 16.5.7 Interrupt Control
      8. 16.5.8 Shadow Load and Lockout Control
      9. 16.5.9 APWM Mode Operation
    6. 16.6 Application of the eCAP Module
      1. 16.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 16.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 16.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 16.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 16.7 Application of the APWM Mode
      1. 16.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 16.8 Software
      1. 16.8.1 ECAP Examples
        1. 16.8.1.1 eCAP APWM Example
        2. 16.8.1.2 eCAP Capture PWM Example
    9. 16.9 ECAP Registers
      1. 16.9.1 ECAP Base Address Table
      2. 16.9.2 ECAP_REGS Registers
  19. 17Enhanced Quadrature Encoder Pulse (eQEP)
    1. 17.1  Introduction
      1. 17.1.1 EQEP Related Collateral
    2. 17.2  Configuring Device Pins
    3. 17.3  Description
      1. 17.3.1 EQEP Inputs
      2. 17.3.2 Functional Description
      3. 17.3.3 eQEP Memory Map
    4. 17.4  Quadrature Decoder Unit (QDU)
      1. 17.4.1 Position Counter Input Modes
        1. 17.4.1.1 Quadrature Count Mode
        2. 17.4.1.2 Direction-Count Mode
        3. 17.4.1.3 Up-Count Mode
        4. 17.4.1.4 Down-Count Mode
      2. 17.4.2 eQEP Input Polarity Selection
      3. 17.4.3 Position-Compare Sync Output
    5. 17.5  Position Counter and Control Unit (PCCU)
      1. 17.5.1 Position Counter Operating Modes
        1. 17.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 17.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 17.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 17.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 17.5.2 Position Counter Latch
        1. 17.5.2.1 Index Event Latch
        2. 17.5.2.2 Strobe Event Latch
      3. 17.5.3 Position Counter Initialization
      4. 17.5.4 eQEP Position-compare Unit
    6. 17.6  eQEP Edge Capture Unit
    7. 17.7  eQEP Watchdog
    8. 17.8  eQEP Unit Timer Base
    9. 17.9  QMA Module
      1. 17.9.1 Modes of Operation
        1. 17.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 17.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 17.9.2 Interrupt and Error Generation
    10. 17.10 eQEP Interrupt Structure
    11. 17.11 Software
      1. 17.11.1 EQEP Examples
        1. 17.11.1.1 Frequency Measurement Using eQEP
        2. 17.11.1.2 Position and Speed Measurement Using eQEP
        3. 17.11.1.3 Frequency Measurement Using eQEP via unit timeout interrupt
        4. 17.11.1.4 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 17.12 EQEP Registers
      1. 17.12.1 EQEP Base Address Table
      2. 17.12.2 EQEP_REGS Registers
  20. 18Universal Asynchronous Receiver/Transmitter (UART)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Functional Description
      1. 18.2.1 Transmit and Receive Logic
      2. 18.2.2 Baud-Rate Generation
      3. 18.2.3 Data Transmission
      4. 18.2.4 Serial IR (SIR)
      5. 18.2.5 9-Bit UART Mode
      6. 18.2.6 FIFO Operation
      7. 18.2.7 Interrupts
      8. 18.2.8 Loopback Operation
      9. 18.2.9 DMA Operation
        1. 18.2.9.1 Receiving Data Using UART with DMA
        2. 18.2.9.2 Transmitting Data Using UART with DMA
    3. 18.3 Initialization and Configuration
    4. 18.4 Software
      1. 18.4.1 UART Examples
        1. 18.4.1.1 UART Echoback
        2. 18.4.1.2 UART Loopback
        3. 18.4.1.3 UART Loopback with interrupt
        4. 18.4.1.4 UART Digital Loopback with DMA
    5. 18.5 UART Registers
      1. 18.5.1 UART Base Address Table
      2. 18.5.2 UART_REGS Registers
      3. 18.5.3 UART_REGS_WRITE Registers
  21. 19Serial Peripheral Interface (SPI)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 Block Diagram
    2. 19.2 System-Level Integration
      1. 19.2.1 SPI Module Signals
      2. 19.2.2 Configuring Device Pins
        1. 19.2.2.1 GPIOs Required for High-Speed Mode
      3. 19.2.3 SPI Interrupts
      4. 19.2.4 DMA Support
    3. 19.3 SPI Operation
      1. 19.3.1  Introduction to Operation
      2. 19.3.2  Controller Mode
      3. 19.3.3  Peripheral Mode
      4. 19.3.4  Data Format
        1. 19.3.4.1 Transmission of Bit from SPIRXBUF
      5. 19.3.5  Baud Rate Selection
        1. 19.3.5.1 Baud Rate Determination
        2. 19.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 19.3.6  SPI Clocking Schemes
      7. 19.3.7  SPI FIFO Description
      8. 19.3.8  SPI DMA Transfers
        1. 19.3.8.1 Transmitting Data Using SPI with DMA
        2. 19.3.8.2 Receiving Data Using SPI with DMA
      9. 19.3.9  SPI High-Speed Mode
      10. 19.3.10 SPI 3-Wire Mode Description
    4. 19.4 Programming Procedure
      1. 19.4.1 Initialization Upon Reset
      2. 19.4.2 Configuring the SPI
      3. 19.4.3 Configuring the SPI for High-Speed Mode
      4. 19.4.4 Data Transfer Example
      5. 19.4.5 SPI 3-Wire Mode Code Examples
        1. 19.4.5.1 3-Wire Controller Mode Transmit
        2.       679
          1. 19.4.5.2.1 3-Wire Controller Mode Receive
        3.       681
          1. 19.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       683
          1. 19.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 19.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 19.5 Software
      1. 19.5.1 SPI Examples
        1. 19.5.1.1 SPI Digital Loopback
        2. 19.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 19.5.1.3 SPI Digital Loopback with DMA
        4. 19.5.1.4 SPI EEPROM
        5. 19.5.1.5 SPI DMA EEPROM
    6. 19.6 SPI Registers
      1. 19.6.1 SPI Base Address Table
      2. 19.6.2 SPI_REGS Registers
  22. 20Inter-Integrated Circuit Module (I2C)
    1. 20.1 Introduction
      1. 20.1.1 I2C Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Features Not Supported
      4. 20.1.4 Functional Overview
      5. 20.1.5 Clock Generation
      6. 20.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 20.1.6.1 Formula for the Controller Clock Period
    2. 20.2 Configuring Device Pins
    3. 20.3 I2C Module Operational Details
      1. 20.3.1  Input and Output Voltage Levels
      2. 20.3.2  Selecting Pullup Resistors
      3. 20.3.3  Data Validity
      4. 20.3.4  Operating Modes
      5. 20.3.5  I2C Module START and STOP Conditions
      6. 20.3.6  Non-repeat Mode versus Repeat Mode
      7. 20.3.7  Serial Data Formats
        1. 20.3.7.1 7-Bit Addressing Format
        2. 20.3.7.2 10-Bit Addressing Format
        3. 20.3.7.3 Free Data Format
        4. 20.3.7.4 Using a Repeated START Condition
      8. 20.3.8  Clock Synchronization
      9. 20.3.9  Clock Stretching
      10. 20.3.10 Arbitration
      11. 20.3.11 Digital Loopback Mode
      12. 20.3.12 NACK Bit Generation
    4. 20.4 Interrupt Requests Generated by the I2C Module
      1. 20.4.1 Basic I2C Interrupt Requests
      2. 20.4.2 I2C FIFO Interrupts
    5. 20.5 Resetting or Disabling the I2C Module
    6. 20.6 Software
      1. 20.6.1 I2C Registers to Driverlib Functions
      2. 20.6.2 I2C Examples
        1. 20.6.2.1 C28x-I2C Library source file for FIFO interrupts
        2. 20.6.2.2 C28x-I2C Library source file for FIFO using polling
        3. 20.6.2.3 I2C Digital Loopback with FIFO Interrupts
        4. 20.6.2.4 I2C EEPROM
        5. 20.6.2.5 I2C EEPROM
        6. 20.6.2.6 I2C EEPROM
    7. 20.7 I2C Registers
      1. 20.7.1 I2C Base Address Table
      2. 20.7.2 I2C_REGS Registers
  23. 21Serial Communications Interface (SCI)
    1. 21.1  Introduction
      1. 21.1.1 Features
      2. 21.1.2 SCI Related Collateral
      3. 21.1.3 Block Diagram
    2. 21.2  Architecture
    3. 21.3  SCI Module Signal Summary
    4. 21.4  Configuring Device Pins
    5. 21.5  Multiprocessor and Asynchronous Communication Modes
    6. 21.6  SCI Programmable Data Format
    7. 21.7  SCI Multiprocessor Communication
      1. 21.7.1 Recognizing the Address Byte
      2. 21.7.2 Controlling the SCI TX and RX Features
      3. 21.7.3 Receipt Sequence
    8. 21.8  Idle-Line Multiprocessor Mode
      1. 21.8.1 Idle-Line Mode Steps
      2. 21.8.2 Block Start Signal
      3. 21.8.3 Wake-Up Temporary (WUT) Flag
        1. 21.8.3.1 Sending a Block Start Signal
      4. 21.8.4 Receiver Operation
    9. 21.9  Address-Bit Multiprocessor Mode
      1. 21.9.1 Sending an Address
    10. 21.10 SCI Communication Format
      1. 21.10.1 Receiver Signals in Communication Modes
      2. 21.10.2 Transmitter Signals in Communication Modes
    11. 21.11 SCI Port Interrupts
      1. 21.11.1 Break Detect
    12. 21.12 SCI Baud Rate Calculations
    13. 21.13 SCI Enhanced Features
      1. 21.13.1 SCI FIFO Description
      2. 21.13.2 SCI Auto-Baud
      3. 21.13.3 Autobaud-Detect Sequence
    14. 21.14 Software
      1. 21.14.1 SCI Examples
        1. 21.14.1.1 Tune Baud Rate via UART Example
        2. 21.14.1.2 SCI FIFO Digital Loop Back
        3. 21.14.1.3 SCI Digital Loop Back with Interrupts
        4. 21.14.1.4 SCI Echoback
        5. 21.14.1.5 stdout redirect example
    15. 21.15 SCI Registers
      1. 21.15.1 SCI Base Address Table
      2. 21.15.2 SCI_REGS Registers
  24. 22Revision History

15.12.3 MCPWM_2CH_REGS Registers

Table 15-84 lists the memory-mapped registers for the MCPWM_2CH_REGS registers. All register offset addresses not listed in Table 15-84 should be considered as reserved locations and the register contents should not be modified.

Table 15-84 MCPWM_2CH_REGS Registers
OffsetAcronymRegister NameWrite Protection
0hREVISIONIP revision id register
8hTBCTLTime base control register
AhTBPRDTime base period register
ChTBPRDSTime base period shadow register
EhTBPHSTime base phase offset register
10hTBSTSTime base status register
12hTBSTSCLRTime base status clear register
14hTBCTRTime base counter register
18hCMPCTLCounter compare control register
20hCMPCCounter compare C register
22hCMPDCounter compare D register
24hCMPCSCounter compare C shadow register
26hCMPDSCounter compare D shadow register
28hAQCTLAction qualifier control register
30hSOCENStart of conversion enable
32hSOCSELStart of conversion selection
34hSOCPERIODStart of conversion period
36hSOCCNTStart of conversion count
38hSOCFLAGStart of conversion flag
3AhSOCCLRStart of conversion clear
40hETSELEvent trigger selection
42hETPERIODEvent trigger period
44hETCNTEvent trigger count
48hINTENInterrupt enableEALLOW
4AhINTFLAGInterrupt flag
4ChINTCLRInterrupt clearEALLOW
4EhINTFRCInterrupt forceEALLOW
50hTZSELTrip Zone selectionEALLOW
56hTZCTLTrip Zone controlEALLOW
58hTZCBCOSTFLAGTrip zone CBCOST flag
5AhTZCBCOSTCLRTrip zone CBCOST flag clearEALLOW
60hDBCTLDead band control register
68hDBFEDDead band fall edge delay
6AhDBREDDead band rise edge delay
6ChDBFEDSDead band fall edge delay shadow register
6EhDBREDSDead band rise edge delay shadow register
78hGLDCTLGlobal load control registerEALLOW
7AhGLDOSHTCTLGlobal load one shot control register
7ChGLDOSHTSTSGlobal load one shot status register
80hPWM1_CMPAPWM1 counter compare A register
82hPWM1_CMPASPWM1 counter compare A shadow register
84hPWM1_CMPBPWM1 counter compare B register
86hPWM1_CMPBSPWM1 counter compare B shadow register
90hPWM1_AQCTLAPWM1 action qualifier A register
92hPWM1_AQCTLASPWM1 action qualifier A shadow register
94hPWM1_AQCTLBPWM1 action qualifier B register
96hPWM1_AQCTLBSPWM1 action qualifier B shadow register
98hPWM1_AQSFRCPWM1 action qualifier software force
9AhPWM1_AQOTSFRCPWM1 action qualifier one time software force

Complex bit access types are encoded to fit into small table cells. Table 15-85 shows the codes that are used for access types in this section.

Table 15-85 MCPWM_2CH_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

15.12.3.1 REVISION Register (Offset = 0h) [Reset = 00000004h]

REVISION is shown in Figure 15-109 and described in Table 15-86.

Return to the Summary Table.

IP revision id register

Figure 15-109 REVISION Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCAP_PRESENTCMPCD_PRESENTPWM3_PRESENTPWM2_PRESENT
R-0-0hR-0hR-1hR-0hR-0h
Table 15-86 REVISION Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3CAP_PRESENTR0hThis hardcoded field defines the presence of Capture mode feature.

Reset type: SYSRSn

2CMPCD_PRESENTR1hThis hardcoded field defines the presence of Compare C and D registers.

Reset type: SYSRSn

1PWM3_PRESENTR0hThis hardcoded field defines the presence of PWM3 channels.

Reset type: SYSRSn

0PWM2_PRESENTR0hThis hardcoded field defines the presence of PWM2 channels.

Reset type: SYSRSn

15.12.3.2 TBCTL Register (Offset = 8h) [Reset = 00000002h]

TBCTL is shown in Figure 15-110 and described in Table 15-87.

Return to the Summary Table.

Time base control register

Figure 15-110 TBCTL Register
3130292827262524
RESERVEDSYNCISELSYNCPERSEL
R-0-0hR/W-0hR/W-0h
2322212019181716
SYNCPERSELFREE_SOFTRESERVEDSYNCOSEL
R/W-0hR/W-0hR-0-0hR/W-0h
15141312111098
SWSYNCRESERVEDPHSDIRPHSENRESERVEDPRDLD
R-0/W1S-0hR-0-0hR/W-0hR/W-0hR-0-0hR/W-0h
76543210
RESERVEDCLKDIVCTRMODE
R-0-0hR/W-0hR/W-2h
Table 15-87 TBCTL Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR-00hReserved
29-25SYNCISELR/W0hThese bits determines the source of SYNCIN signal.
0x0 : Disabled using SOC tieoff.
0x1-0x1F : Refer to PWM chapter of TRM.

Reset type: SYSRSn

24-22SYNCPERSELR/W0hSync peripheral Select

000: Reserved (Disabled)
001: Reserved (Disabled)
010: CTR = PRD
011: CTR = 0
100: CTR = CMPC, Count direction Up
101: CTR = CMPC, Count direction Down
110: CTR = CMPD, Count direction Up
111: CTR = CMPD, Count direction Down

Reset type: SYSRSn

21-20FREE_SOFTR/W0hEmulation Mode Bits. These bits select the behavior of the time-base counter during emulation events

00: Stop after the next time-base counter increment or decrement
01: Stop when counter completes a whole cycle:
- Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD)
- Up-down-count mode: stop when the time-base counter = 0x00 (TBCTR = 0x00)
1x: Free run

Reset type: SYSRSn

19RESERVEDR-00hReserved
18-16SYNCOSELR/W0hSync Output Select

000: SWFSYNC
001: CTR = zero: Time-base counter equal to zero (TBCTR = 0x00)
010: CTR = CMPC : Time-base counter equal to counter-compare C (TBCTR = CMPC)
011: CTR = CMPD : Time-base counter equal to counter-compare D (TBCTR = CMPD)
1xx: Disabled MCPWMxSYNCO sync signal

Reset type: SYSRSn

15SWSYNCR-0/W1S0hSoftware Forced Sync Pulse

0: Writing a 0 has no effect and reads always return a 0.
1: Writing a 1 forces a one-time synchronization pulse to be generated.

Reset type: SYSRSn

14-12RESERVEDR-00hReserved
11PHSDIRR/W0hPhase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-count mode. In the up-count mode, this bit is ignored.

The bit indicates the direction of the time-base counter (TBCTR) after a sync event occurs and a new phase value is loaded from the phase (TBPHS) register.
0: Count down after the sync event.
1: Count up after the sync event.

Reset type: SYSRSn

10PHSENR/W0hLoad Phase register to time-base counter(TBCNTR)

0: Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS).
1: Allow Counter to be loaded from the Phase register (TBPHS) when an MCPWMxSYNCI input signal occurs or a software-forced sync (SWSYNC).

Reset type: SYSRSn

9RESERVEDR-00hReserved
8PRDLDR/W0hShadow to Active load of TBPRD register

0: Shadow to Active Load of TBPRD occurs when TBCTR = 0
1 : Disabled shadow to active load of TBPRD

Reset type: SYSRSn

7-6RESERVEDR-00hReserved
5-2CLKDIVR/W0hTime Base Clock Pre-Scale Bits
These bits select the time base clock pre-scale value (TBCLK = MCPWMCLK/CLKDIV):

0000: /1 (default on reset)
0001: /2
0010: /4
0011: /8
0100: /16
0101: /32
0110: /64
0111: /128
1000: /256
1001: /512
1010: /1024
1011: /2048
1100: /4096
1101: /8192
1110: /16384
1111: /32768

Reset type: SYSRSn

1-0CTRMODER/W2hThe time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change. These bits set the time-base counter mode of operation as follows:
00: Up-count mode
01: Up-down count mode
1x: Freeze counter operation (default on reset)

Reset type: SYSRSn

15.12.3.3 TBPRD Register (Offset = Ah) [Reset = 00000000h]

TBPRD is shown in Figure 15-111 and described in Table 15-88.

Return to the Summary Table.

Time base period register

Figure 15-111 TBPRD Register
313029282726252423222120191817161514131211109876543210
RESERVEDTBPRD
R-0-0hR/W-0h
Table 15-88 TBPRD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0TBPRDR/W0hTime Base Period Register

These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed.
- If TBCTL[PRDLD] = 0, then the shadow is enabled. This register will also loaded from the shadow register when the time-base counter equals zero.
- If TBCTL[PRDLD] = 1, then the shadow is disabled.

Reset type: SYSRSn

15.12.3.4 TBPRDS Register (Offset = Ch) [Reset = 00000000h]

TBPRDS is shown in Figure 15-112 and described in Table 15-89.

Return to the Summary Table.

Time base period shadow register

Figure 15-112 TBPRDS Register
313029282726252423222120191817161514131211109876543210
RESERVEDTBPRDS
R-0-0hR/W-0h
Table 15-89 TBPRDS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0TBPRDSR/W0hTime Base Period Shadow Register

The value in the TBPRDS register is loaded into TBPRD register when shadow to active load occurs.

Reset type: SYSRSn

15.12.3.5 TBPHS Register (Offset = Eh) [Reset = 00000000h]

TBPHS is shown in Figure 15-113 and described in Table 15-90.

Return to the Summary Table.

Time base phase offset register

Figure 15-113 TBPHS Register
313029282726252423222120191817161514131211109876543210
RESERVEDTBPHS
R-0-0hR/W-0h
Table 15-90 TBPHS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0TBPHSR/W0hPhase Offset Register

These bits set time-base counter phase of the PWM relative to the sync (MCPWMxSYNCI / SWFSYNC)

- If TBCTL[PHSEN] = 0, then the sync event is ignored.
- If TBCTL[PHSEN] = 1, then the time-base counter (TBCTR) will be loaded with the phase (TBPHS) when a sync event occurs. The sync event can be initiated by the input sync signal (MCPWMxSYNCI) or by a software forced sync.

Reset type: SYSRSn

15.12.3.6 TBSTS Register (Offset = 10h) [Reset = 00000000h]

TBSTS is shown in Figure 15-114 and described in Table 15-91.

Return to the Summary Table.

Time base status register

Figure 15-114 TBSTS Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSYNCICTRDIR
R-0-0hR-0hR-0h
Table 15-91 TBSTS Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR-00hReserved
1SYNCIR0hInput Synchronization Latched Status Bit

0: No external sync event has occurred.
1: External sync event has occurred (MCPWMxSYNCI).

Reset type: SYSRSn

0CTRDIRR0hTime Base Counter Direction Status Bit

0: Time-Base Counter is currently counting up.
1: Time-Base Counter is currently counting down.

Note: This bit is only valid when the counter is not frozen.

Reset type: SYSRSn

15.12.3.7 TBSTSCLR Register (Offset = 12h) [Reset = 00000000h]

TBSTSCLR is shown in Figure 15-115 and described in Table 15-92.

Return to the Summary Table.

Time base status clear register

Figure 15-115 TBSTSCLR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSYNCIRESERVED
R-0-0hR-0/W1S-0hR-0-0h
Table 15-92 TBSTSCLR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR-00hReserved
1SYNCIR-0/W1S0hInput Synchronization Latched Status Clear

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TBSTS[SYNCI] bit.

Reset type: SYSRSn

0RESERVEDR-00hReserved

15.12.3.8 TBCTR Register (Offset = 14h) [Reset = 00000000h]

TBCTR is shown in Figure 15-116 and described in Table 15-93.

Return to the Summary Table.

Time base counter register

Figure 15-116 TBCTR Register
313029282726252423222120191817161514131211109876543210
RESERVEDTBCTR
R-0-0hR/W-0h
Table 15-93 TBCTR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0TBCTRR/W0hTime Base Counter Register

Reset type: SYSRSn

15.12.3.9 CMPCTL Register (Offset = 18h) [Reset = 00000000h]

CMPCTL is shown in Figure 15-117 and described in Table 15-94.

Return to the Summary Table.

Counter compare control register

Figure 15-117 CMPCTL Register
3130292827262524
RESERVEDLOADDMODELOADCMODE
R-0-0hR/W-0hR/W-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDPWM1_LOADBMODEPWM1_LOADAMODE
R-0-0hR/W-0hR/W-0h
Table 15-94 CMPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR-00hReserved
27-26LOADDMODER/W0hShadow to Active load of CMPD register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: This field can be present only when the configuration parameter CCM_CD_PRESENT = 1

Reset type: SYSRSn

25-24LOADCMODER/W0hShadow to Active load of CMPC register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: This field can be present only when the configuration parameter CCM_CD_PRESENT = 1

Reset type: SYSRSn

23-4RESERVEDR-00hReserved
3-2PWM1_LOADBMODER/W0hShadow to Active load of PWM1_CMPB register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

1-0PWM1_LOADAMODER/W0hShadow to Active load of PWM1_CMPA register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

15.12.3.10 CMPC Register (Offset = 20h) [Reset = 00000000h]

CMPC is shown in Figure 15-118 and described in Table 15-95.

Return to the Summary Table.

Counter compare C register

Figure 15-118 CMPC Register
313029282726252423222120191817161514131211109876543210
RESERVEDCMPC
R-0-0hR/W-0h
Table 15-95 CMPC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0CMPCR/W0hCompare C register

The value in the CMPC register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a 'time-base counter equal to counter compare C' event.

Shadowing of this register is enabled and disabled by the CMPCTL[LOADCMODE] field. By default this register is shadowed.

Reset type: SYSRSn

15.12.3.11 CMPD Register (Offset = 22h) [Reset = 00000000h]

CMPD is shown in Figure 15-119 and described in Table 15-96.

Return to the Summary Table.

Counter compare D register

Figure 15-119 CMPD Register
313029282726252423222120191817161514131211109876543210
RESERVEDCMPD
R-0-0hR/W-0h
Table 15-96 CMPD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0CMPDR/W0hCompare D register

The value in the CMPD register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a 'time-base counter equal to counter compare D' event.

Shadowing of this register is enabled and disabled by the CMPCTL[LOADDMODE] field. By default this register is shadowed.

Reset type: SYSRSn

15.12.3.12 CMPCS Register (Offset = 24h) [Reset = 00000000h]

CMPCS is shown in Figure 15-120 and described in Table 15-97.

Return to the Summary Table.

Counter compare C shadow register

Figure 15-120 CMPCS Register
313029282726252423222120191817161514131211109876543210
RESERVEDCMPCS
R-0-0hR/W-0h
Table 15-97 CMPCS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0CMPCSR/W0hCompare C Shadow Register

The value in the CMPCS register is loaded into CMPC register when shadow to active load occurs.

Reset type: SYSRSn

15.12.3.13 CMPDS Register (Offset = 26h) [Reset = 00000000h]

CMPDS is shown in Figure 15-121 and described in Table 15-98.

Return to the Summary Table.

Counter compare D shadow register

Figure 15-121 CMPDS Register
313029282726252423222120191817161514131211109876543210
RESERVEDCMPDS
R-0-0hR/W-0h
Table 15-98 CMPDS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0CMPDSR/W0hCompare D Shadow Register

The value in the CMPDS register is loaded into CMPD register when shadow to active load occurs.

Reset type: SYSRSn

15.12.3.14 AQCTL Register (Offset = 28h) [Reset = 00000000h]

AQCTL is shown in Figure 15-122 and described in Table 15-99.

Return to the Summary Table.

Action qualifier control register

Figure 15-122 AQCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDPWM1_LDAQBMODEPWM1_LDAQAMODE
R-0-0hR/W-0hR/W-0h
Table 15-99 AQCTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3-2PWM1_LDAQBMODER/W0hShadow to Active load of PWM1_AQCTLB register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

1-0PWM1_LDAQAMODER/W0hShadow to Active load of PWM1_AQCTLA register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

15.12.3.15 SOCEN Register (Offset = 30h) [Reset = 00000000h]

SOCEN is shown in Figure 15-123 and described in Table 15-100.

Return to the Summary Table.

Start of conversion enable

Figure 15-123 SOCEN Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDSOCB_ENABLESOCA_ENABLE
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-100 SOCEN Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1SOCB_ENABLER/W0hSOCB Selection Enable

0 - SOCB disable
1- SOCB enable

Reset type: SYSRSn

0SOCA_ENABLER/W0hSOCA Selection Enable

0 - SOCA disable
1- SOCA enable

Reset type: SYSRSn

15.12.3.16 SOCSEL Register (Offset = 32h) [Reset = 00000000h]

SOCSEL is shown in Figure 15-124 and described in Table 15-101.

Return to the Summary Table.

Start of conversion selection

Figure 15-124 SOCSEL Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR-0-0hR/W-0h
1514131211109876543210
RESERVEDSOCB_SELRESERVEDSOCA_SEL
R-0-0hR/W-0hR-0-0hR/W-0h
Table 15-101 SOCSEL Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR-00hReserved
28-24RESERVEDR/W0hReserved
23-21RESERVEDR-00hReserved
20-16RESERVEDR/W0hReserved
15-13RESERVEDR-00hReserved
12-8SOCB_SELR/W0hSOCB Selection Options

These bits determine when SOCB pulse will be generated.

00000: Reserved (SOC B disabled)
00001: Reserved (SOC B disabled)
00010: Enable event time-base counter equal to zero (TBCTR = 0x0000)
00011: Enable event time-base counter equal to period (TBCTR = TBPRD)
00100: Enable event time-base counter equal to zero or period (TBCTR = 0x00 or TBCTR = TBPRD)
00101 - 00111: Reserved (SOC B disabled)
01000: Enable event time-base counter equal to CMPC when the timer is incrementing
01001: Enable event time-base counter equal to CMPD when the timer is incrementing
01010: Enable event time-base counter equal to PWM1_CMPA when the timer is incrementing
01011: Enable event time-base counter equal to PWM1_CMPB when the timer is incrementing
01100: Enable event time-base counter equal to PWM2_CMPA when the timer is incrementing
01101: Enable event time-base counter equal to PWM2_CMPB when the timer is incrementing
01110: Enable event time-base counter equal to PWM3_CMPA when the timer is incrementing
01111: Enable event time-base counter equal to PWM3_CMPB when the timer is incrementing
10000: Enable event time-base counter equal to CMPC when the timer is decrementing
10001: Enable event time-base counter equal to CMPD when the timer is decrementing
10010: Enable event time-base counter equal to PWM1_CMPA when the timer is decrementing
10011: Enable event time-base counter equal to PWM1_CMPB when the timer is decrementing
10100: Enable event time-base counter equal to PWM2_CMPA when the timer is decrementing
10101: Enable event time-base counter equal to PWM2_CMPB when the timer is decrementing
10110: Enable event time-base counter equal to PWM3_CMPA when the timer is decrementing
10111: Enable event time-base counter equal to PWM3_CMPB when the timer is decrementing
11000 - 11111: Reserved (SOC B disabled)

Reset type: SYSRSn

7-5RESERVEDR-00hReserved
4-0SOCA_SELR/W0hSOCA Selection Options

These bits determine when SOCA pulse will be generated.

00000: Reserved (SOC A disabled)
00001: Reserved (SOC A disabled)
00010: Enable event time-base counter equal to zero (TBCTR = 0x0000)
00011: Enable event time-base counter equal to period (TBCTR = TBPRD)
00100: Enable event time-base counter equal to zero or period (TBCTR = 0x00 or TBCTR = TBPRD)
00101 - 00111: Reserved (SOC A disabled)
01000: Enable event time-base counter equal to CMPC when the timer is incrementing
01001: Enable event time-base counter equal to CMPD when the timer is incrementing
01010: Enable event time-base counter equal to PWM1_CMPA when the timer is incrementing
01011: Enable event time-base counter equal to PWM1_CMPB when the timer is incrementing
01100: Enable event time-base counter equal to PWM2_CMPA when the timer is incrementing
01101: Enable event time-base counter equal to PWM2_CMPB when the timer is incrementing
01110: Enable event time-base counter equal to PWM3_CMPA when the timer is incrementing
01111: Enable event time-base counter equal to PWM3_CMPB when the timer is incrementing
10000: Enable event time-base counter equal to CMPC when the timer is decrementing
10001: Enable event time-base counter equal to CMPD when the timer is decrementing
10010: Enable event time-base counter equal to PWM1_CMPA when the timer is decrementing
10011: Enable event time-base counter equal to PWM1_CMPB when the timer is decrementing
10100: Enable event time-base counter equal to PWM2_CMPA when the timer is decrementing
10101: Enable event time-base counter equal to PWM2_CMPB when the timer is decrementing
10110: Enable event time-base counter equal to PWM3_CMPA when the timer is decrementing
10111: Enable event time-base counter equal to PWM3_CMPB when the timer is decrementing
11000 - 11111: Reserved (SOC A disabled)

Reset type: SYSRSn

15.12.3.17 SOCPERIOD Register (Offset = 34h) [Reset = 00000000h]

SOCPERIOD is shown in Figure 15-125 and described in Table 15-102.

Return to the Summary Table.

Start of conversion period

Figure 15-125 SOCPERIOD Register
3130292827262524
RESERVEDRESERVED
R-0-0hR/W-0h
2322212019181716
RESERVEDRESERVED
R-0-0hR/W-0h
15141312111098
RESERVEDSOCB_PERIOD
R-0-0hR/W-0h
76543210
RESERVEDSOCA_PERIOD
R-0-0hR/W-0h
Table 15-102 SOCPERIOD Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR-00hReserved
26-24RESERVEDR/W0hReserved
23-19RESERVEDR-00hReserved
18-16RESERVEDR/W0hReserved
15-11RESERVEDR-00hReserved
10-8SOCB_PERIODR/W0hSOCB Period

These bits determine how many selected SOCSEL[SOCB_SEL] events need to occur before an SOCB pulse is generated. To be generated, the pulse must be enabled (SOCEN[SOCB_ENABLE] = 1). The SOCB pulse will be generated even if the status flag is set from a previous start of conversion (SOCFLAG[SOCB] = 1). Once the SOCB pulse is generated, the SOCCNT[SOCB_CNT] bits will automatically be cleared.

Reset type: SYSRSn

7-3RESERVEDR-00hReserved
2-0SOCA_PERIODR/W0hSOCA Period

These bits determine how many selected SOCSEL[SOCA_SEL] events need to occur before an SOCA pulse is generated. To be generated, the pulse must be enabled (SOCEN[SOCA_ENABLE] = 1). The SOCA pulse will be generated even if the status flag is set from a previous start of conversion (SOCFLAG[SOCA] = 1). Once the SOCA pulse is generated, the SOCCNT[SOCA_CNT] bits will automatically be cleared.

Reset type: SYSRSn

15.12.3.18 SOCCNT Register (Offset = 36h) [Reset = 00000000h]

SOCCNT is shown in Figure 15-126 and described in Table 15-103.

Return to the Summary Table.

Start of conversion count

Figure 15-126 SOCCNT Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR-0hR-0-0hR-0h
1514131211109876543210
RESERVEDSOCB_CNTRESERVEDSOCA_CNT
R-0-0hR-0hR-0-0hR-0h
Table 15-103 SOCCNT Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR-00hReserved
26-24RESERVEDR0hReserved
23-19RESERVEDR-00hReserved
18-16RESERVEDR0hReserved
15-11RESERVEDR-00hReserved
10-8SOCB_CNTR0hSOC B Counter Register

These bits indicate how many selected SOCSEL[SOCB_SEL] events have occurred. These bits are automatically cleared when a SOCB pulse is generated.

Reset type: SYSRSn

7-3RESERVEDR-00hReserved
2-0SOCA_CNTR0hSOC A Counter Register

These bits indicate how many selected SOCSEL[SOCA_SEL] events have occurred. These bits are automatically cleared when a SOCA pulse is generated.

Reset type: SYSRSn

15.12.3.19 SOCFLAG Register (Offset = 38h) [Reset = 00000000h]

SOCFLAG is shown in Figure 15-127 and described in Table 15-104.

Return to the Summary Table.

Start of conversion flag

Figure 15-127 SOCFLAG Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDSOCBSOCA
R-0-0hR-0hR-0hR-0hR-0h
Table 15-104 SOCFLAG Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3RESERVEDR0hReserved
2RESERVEDR0hReserved
1SOCBR0hLatched SOC B Status Flag

SOCB output will continue to pulse even if the flag bit is set.

0: Indicates no event occurred
1: Indicates that a start of conversion pulse was generated on SOCB. The SOCB output will continue to be generated even if the flag bit is set.

Reset type: SYSRSn

0SOCAR0hLatched SOC A Status Flag

SOCA output will continue to pulse even if the flag bit is set.

0: Indicates no event occurred
1: Indicates that a start of conversion pulse was generated on SOCA. The SOCA output will continue to be generated even if the flag bit is set.

Reset type: SYSRSn

15.12.3.20 SOCCLR Register (Offset = 3Ah) [Reset = 00000000h]

SOCCLR is shown in Figure 15-128 and described in Table 15-105.

Return to the Summary Table.

Start of conversion clear

Figure 15-128 SOCCLR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDSOCBSOCA
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 15-105 SOCCLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3RESERVEDR-0/W1S0hReserved
2RESERVEDR-0/W1S0hReserved
1SOCBR-0/W1S0hClear SOC B Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the SOCFLAG[SOCB] bit.

Reset type: SYSRSn

0SOCAR-0/W1S0hClear SOC A Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the SOCFLAG[SOCA] bit.

Reset type: SYSRSn

15.12.3.21 ETSEL Register (Offset = 40h) [Reset = 00000000h]

ETSEL is shown in Figure 15-129 and described in Table 15-106.

Return to the Summary Table.

Event trigger selection

Figure 15-129 ETSEL Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDET2_SELRESERVEDET1_SEL
R-0-0hR/W-0hR-0-0hR/W-0h
Table 15-106 ETSEL Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR-00hReserved
12-8ET2_SELR/W0hEvent trigger2 Selection Options

These bits determine when event trigger pulse will be generated.

00000: Reserved (ET2 Disabled)
00001: Reserved (ET2 Disabled)
00010: Enable event time-base counter equal to zero (TBCTR = 0x0000)
00011: Enable event time-base counter equal to period (TBCTR = TBPRD)
00100: Enable event time-base counter equal to zero or period (TBCTR = 0x00 or TBCTR = TBPRD)
00101 - 00111: Reserved (ET2 Disabled)
01000: Enable event time-base counter equal to CMPC when the timer is incrementing
01001: Enable event time-base counter equal to CMPD when the timer is incrementing
01010: Enable event time-base counter equal to PWM1_CMPA when the timer is incrementing
01011: Enable event time-base counter equal to PWM1_CMPB when the timer is incrementing
01100: Enable event time-base counter equal to PWM2_CMPA when the timer is incrementing
01101: Enable event time-base counter equal to PWM2_CMPB when the timer is incrementing
01110: Enable event time-base counter equal to PWM3_CMPA when the timer is incrementing
01111: Enable event time-base counter equal to PWM3_CMPB when the timer is incrementing
10000: Enable event time-base counter equal to CMPC when the timer is decrementing
10001: Enable event time-base counter equal to CMPD when the timer is decrementing
10010: Enable event time-base counter equal to PWM1_CMPA when the timer is decrementing
10011: Enable event time-base counter equal to PWM1_CMPB when the timer is decrementing
10100: Enable event time-base counter equal to PWM2_CMPA when the timer is decrementing
10101: Enable event time-base counter equal to PWM2_CMPB when the timer is decrementing
10110: Enable event time-base counter equal to PWM3_CMPA when the timer is decrementing
10111: Enable event time-base counter equal to PWM3_CMPB when the timer is decrementing
11000 - 11111: Reserved (ET2 Disabled)

Reset type: SYSRSn

7-5RESERVEDR-00hReserved
4-0ET1_SELR/W0hEvent trigger1 Selection Options

These bits determine when event trigger pulse will be generated.

00000: Reserved (ET1 Disabled)
00001: Reserved (ET1 Disabled)
00010: Enable event time-base counter equal to zero (TBCTR = 0x0000)
00011: Enable event time-base counter equal to period (TBCTR = TBPRD)
00100: Enable event time-base counter equal to zero or period (TBCTR = 0x00 or TBCTR = TBPRD)
00101 - 00111: Reserved (ET1 Disabled)
01000: Enable event time-base counter equal to CMPC when the timer is incrementing
01001: Enable event time-base counter equal to CMPD when the timer is incrementing
01010: Enable event time-base counter equal to PWM1_CMPA when the timer is incrementing
01011: Enable event time-base counter equal to PWM1_CMPB when the timer is incrementing
01100: Enable event time-base counter equal to PWM2_CMPA when the timer is incrementing
01101: Enable event time-base counter equal to PWM2_CMPB when the timer is incrementing
01110: Enable event time-base counter equal to PWM3_CMPA when the timer is incrementing
01111: Enable event time-base counter equal to PWM3_CMPB when the timer is incrementing
10000: Enable event time-base counter equal to CMPC when the timer is decrementing
10001: Enable event time-base counter equal to CMPD when the timer is decrementing
10010: Enable event time-base counter equal to PWM1_CMPA when the timer is decrementing
10011: Enable event time-base counter equal to PWM1_CMPB when the timer is decrementing
10100: Enable event time-base counter equal to PWM2_CMPA when the timer is decrementing
10101: Enable event time-base counter equal to PWM2_CMPB when the timer is decrementing
10110: Enable event time-base counter equal to PWM3_CMPA when the timer is decrementing
10111: Enable event time-base counter equal to PWM3_CMPB when the timer is decrementing
11000 - 11111: Reserved (ET1 Disabled)

Reset type: SYSRSn

15.12.3.22 ETPERIOD Register (Offset = 42h) [Reset = 00000000h]

ETPERIOD is shown in Figure 15-130 and described in Table 15-107.

Return to the Summary Table.

Event trigger period

Figure 15-130 ETPERIOD Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDET2_PERIOD
R-0-0hR/W-0h
76543210
RESERVEDET1_PERIOD
R-0-0hR/W-0h
Table 15-107 ETPERIOD Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR-00hReserved
10-8ET2_PERIODR/W0hThese bits determine how many selected ETSEL[ET2_SEL] events need to occur before an interrupt is generated. If the interrupt status flag is set from a previous interrupt (INTFLG[ET2] = 1) then no interrupt will be generated until the flag is cleared via the INTCLR[ET2] bit. This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is generated, the ETCNT[ET2_CNT] bits will automatically be cleared.

Writing a PERIOD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear.

Writing a PERIOD value that is less than the current counter value will result in an undefined state. If a counter event occurs at the same instant as a new zero or non-zero PERIOD value is written, the counter is incremented.

Reset type: SYSRSn

7-3RESERVEDR-00hReserved
2-0ET1_PERIODR/W0hThese bits determine how many selected ETSEL[ET1_SEL] events need to occur before an interrupt is generated. If the interrupt status flag is set from a previous interrupt (INTFLG[ET1] = 1) then no interrupt will be generated until the flag is cleared via the INTCLR[ET1] bit. This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is generated, the ETCNT[ET1_CNT] bits will automatically be cleared.

Writing a PERIOD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear.

Writing a PERIOD value that is less than the current counter value will result in an undefined state. If a counter event occurs at the same instant as a new zero or non-zero PERIOD value is written, the counter is incremented.

Reset type: SYSRSn

15.12.3.23 ETCNT Register (Offset = 44h) [Reset = 00000000h]

ETCNT is shown in Figure 15-131 and described in Table 15-108.

Return to the Summary Table.

Event trigger count

Figure 15-131 ETCNT Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDET2_CNTRESERVEDET1_CNT
R-0-0hR-0hR-0-0hR-0h
Table 15-108 ETCNT Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR-00hReserved
10-8ET2_CNTR0hEvent trigger2 Counter Register

These bits indicate how many selected ET_SEL[ET2_SEL] events have occurred. These bits are automatically cleared once INTFLAG.ET2 is generated (irrespective of INTEN.ET2 configuration).

Reset type: SYSRSn

7-3RESERVEDR-00hReserved
2-0ET1_CNTR0hEvent trigger1 Counter Register

These bits indicate how many selected ET_SEL[ET1_SEL] events have occurred. These bits are automatically cleared once INTFLAG.ET1 is generated (irrespective of INTEN.ET1 configuration).

Reset type: SYSRSn

15.12.3.24 INTEN Register (Offset = 48h) [Reset = 00000000h]

INTEN is shown in Figure 15-132 and described in Table 15-109.

Return to the Summary Table.

Interrupt enable

Figure 15-132 INTEN Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCNT_OVFET2ET1OSTCBCRESERVED
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0h
Table 15-109 INTEN Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5CNT_OVFR/W0hCounter Overflow Interrupt Enable
1 : Enables CNT_OVF interrupt
0 : Disable CNT_OVF interrupt

Reset type: SYSRSn

4ET2R/W0hEvent Trigger 2 Interrupt Enable
1 : Enables ET2 interrupt
0 : Disable ET2 interrupt

Reset type: SYSRSn

3ET1R/W0hEvent Trigger 1 Interrupt Enable
1 : Enables ET1 interrupt
0 : Disable ET1 interrupt

Reset type: SYSRSn

2OSTR/W0hTrip-zone One-Shot Interrupt Enable
1 : Enables OST interrupt
0 : Disable OST interrupt

Reset type: SYSRSn

1CBCR/W0hTrip-zone Cycle-by-Cycle Interrupt Enable
1 : Enables CBC interrupt
0 : Disable CBC interrupt

Reset type: SYSRSn

0RESERVEDR0hReserved

15.12.3.25 INTFLAG Register (Offset = 4Ah) [Reset = 00000000h]

INTFLAG is shown in Figure 15-133 and described in Table 15-110.

Return to the Summary Table.

Interrupt flag

Figure 15-133 INTFLAG Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCNT_OVFET2ET1OSTCBCINT
R-0-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 15-110 INTFLAG Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5CNT_OVFR0hLatched Status Flag for A Counter Overflow Event
1 : CNT_OVF flag is set
0 : CNT_OVF flag is not set

Reset type: SYSRSn

4ET2R0hLatched Status Flag for A Event Trigger 2 Event
1: ET2 flag is set
0: ET2 flag is not set

Reset type: SYSRSn

3ET1R0hLatched Status Flag for A Event Trigger 1 Event
1: ET1 flag is set
0: ET1 flag is not set

Reset type: SYSRSn

2OSTR0hLatched Status Flag for A One-Shot Trip Event
1: OST flag is set
0: OST flag is not set

Reset type: SYSRSn

1CBCR0hLatched Status Flag for Cycle-By-Cycle Trip Event
1: CBC flag is set
0: CBC flag is not set

Reset type: SYSRSn

0INTR0hGlobal Interrupt Status Flag
1: Global flag is set
0: Global flag is not set

Reset type: SYSRSn

15.12.3.26 INTCLR Register (Offset = 4Ch) [Reset = 00000000h]

INTCLR is shown in Figure 15-134 and described in Table 15-111.

Return to the Summary Table.

Interrupt clear

Figure 15-134 INTCLR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCNT_OVFET2ET1OSTCBCINT
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 15-111 INTCLR Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5CNT_OVFR-0/W1S0hClear Counter Overflow Flag
Writing '1' will clear INTFLAG[CNT_OVF] register.

Reset type: SYSRSn

4ET2R-0/W1S0hClear Event Trigger 2 Flag
Writing '1' will clear INTFLAG[ET2] register.

Reset type: SYSRSn

3ET1R-0/W1S0hClear Event Trigger 1 Flag
Writing '1' will clear INTFLAG[ET1] register.

Reset type: SYSRSn

2OSTR-0/W1S0hClear One-Shot Trip Latch
Writing '1' will clear INTFLAG[OST] register.

Reset type: SYSRSn

1CBCR-0/W1S0hClear Cycle-by-Cycle Trip Latch
Writing '1' will clear INTFLAG[CBC] register.

Reset type: SYSRSn

0INTR-0/W1S0hClear Global Interrupt Flag
Writing '1' will clear INTFLAG[INT] register.

Reset type: SYSRSn

15.12.3.27 INTFRC Register (Offset = 4Eh) [Reset = 00000000h]

INTFRC is shown in Figure 15-135 and described in Table 15-112.

Return to the Summary Table.

Interrupt force

Figure 15-135 INTFRC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCNT_OVFET2ET1OSTCBCRESERVED
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0h
Table 15-112 INTFRC Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5CNT_OVFR-0/W1S0hForce Counter Overflow Interrupt
Writing '1' will set INTFLAG[CNT_OVF] register.

Reset type: SYSRSn

4ET2R-0/W1S0hForce Event Trigger 2 Interrupt
Writing '1' will set INTFLAG[ET2] register.

Reset type: SYSRSn

3ET1R-0/W1S0hForce Event Trigger 1 Interrupt
Writing '1' will set INTFLAG[ET1] register.

Reset type: SYSRSn

2OSTR-0/W1S0hForce One-Shot Trip Interrupt
Writing '1' will set INTFLAG[OST] register.

Reset type: SYSRSn

1CBCR-0/W1S0hForce Cycle-by-Cycle Trip Interrupt
Writing '1' will set INTFLAG[CBC] register.

Reset type: SYSRSn

0RESERVEDR0hReserved

15.12.3.28 TZSEL Register (Offset = 50h) [Reset = 00000000h]

TZSEL is shown in Figure 15-136 and described in Table 15-113.

Return to the Summary Table.

Trip Zone selection

Figure 15-136 TZSEL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
OST8OST7OST6OST5OST4OST3OST2OST1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
CBC8CBC7CBC6CBC5CBC4CBC3CBC2CBC1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-113 TZSEL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR-00hReserved
23OST8R/W0hSelect Trip-zone 8 (TZ8) for OST generation

0: Disable TZ8 as a OST trip source for this MCPWM module
1: Enable TZ8 as a OST trip source for this MCPWM module

Reset type: SYSRSn

22OST7R/W0hSelect Trip-zone 7 (TZ7) for OST generation

0: Disable TZ7 as a OST trip source for this MCPWM module
1: Enable TZ7 as a OST trip source for this MCPWM module

Reset type: SYSRSn

21OST6R/W0hSelect Trip-zone 6 (TZ6) for OST generation

0: Disable TZ6 as a OST trip source for this MCPWM module
1: Enable TZ6 as a OST trip source for this MCPWM module

Reset type: SYSRSn

20OST5R/W0hSelect Trip-zone 5 (TZ5) for OST generation

0: Disable TZ5 as a OST trip source for this MCPWM module
1: Enable TZ5 as a OST trip source for this MCPWM module

Reset type: SYSRSn

19OST4R/W0hSelect Trip-zone 4 (TZ4) for OST generation

0: Disable TZ4 as a OST trip source for this MCPWM module
1: Enable TZ4 as a OST trip source for this MCPWM module

Reset type: SYSRSn

18OST3R/W0hSelect Trip-zone 3 (TZ3) for OST generation

0: Disable TZ3 as a OST trip source for this MCPWM module
1: Enable TZ3 as a OST trip source for this MCPWM module

Reset type: SYSRSn

17OST2R/W0hSelect Trip-zone 2 (TZ2) for OST generation

0: Disable TZ2 as a OST trip source for this MCPWM module
1: Enable TZ2 as a OST trip source for this MCPWM module

Reset type: SYSRSn

16OST1R/W0hSelect Trip-zone 1 (TZ1) for OST generation

0: Disable TZ1 as a OST trip source for this MCPWM module
1: Enable TZ1 as a OST trip source for this MCPWM module

Reset type: SYSRSn

15-8RESERVEDR-00hReserved
7CBC8R/W0hSelect Trip-zone 8 (TZ8) for CBC generation

0: Disable TZ8 as a CBC trip source for this MCPWM module
1: Enable TZ8 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

6CBC7R/W0hSelect Trip-zone 7 (TZ7) for CBC generation

0: Disable TZ7 as a CBC trip source for this MCPWM module
1: Enable TZ7 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

5CBC6R/W0hSelect Trip-zone 6 (TZ6) for CBC generation

0: Disable TZ6 as a CBC trip source for this MCPWM module
1: Enable TZ6 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

4CBC5R/W0hSelect Trip-zone 5 (TZ5) for CBC generation

0: Disable TZ5 as a CBC trip source for this MCPWM module
1: Enable TZ5 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

3CBC4R/W0hSelect Trip-zone 4 (TZ4) for CBC generation

0: Disable TZ4 as a CBC trip source for this MCPWM module
1: Enable TZ4 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

2CBC3R/W0hSelect Trip-zone 3 (TZ3) for CBC generation

0: Disable TZ3 as a CBC trip source for this MCPWM module
1: Enable TZ3 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

1CBC2R/W0hSelect Trip-zone 2 (TZ2) for CBC generation

0: Disable TZ2 as a CBC trip source for this MCPWM module
1: Enable TZ2 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

0CBC1R/W0hSelect Trip-zone 1 (TZ1) for CBC generation

0: Disable TZ1 as a CBC trip source for this MCPWM module
1: Enable TZ1 as a CBC trip source for this MCPWM module

Reset type: SYSRSn

15.12.3.29 TZCTL Register (Offset = 56h) [Reset = 00000010h]

TZCTL is shown in Figure 15-137 and described in Table 15-114.

Return to the Summary Table.

Trip Zone control

Figure 15-137 TZCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCBCPULSETZBTZA
R-0-0hR/W-1hR/W-0hR/W-0h
Table 15-114 TZCTL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5-4CBCPULSER/W1hClear Pulse for Cycle-By-Cycle (CBC) Trip Latch

This bit field determines which pulse clears the CBC trip latch.

00: CBC trip latch is not cleared
01: CTR = ZERO pulse clears CBC trip latch
10: CTR = PRD pulse clears CBC trip latch
11: CTR = ZERO or CTR = PRD pulse clears CBC trip latch

Reset type: SYSRSn

3-2TZBR/W0hTrip action on PWMxB

00: High-impedance (PWMxB = High-impedance state)
01: Force PWMxB to a high state
10: Force PWMxB to a low state
11: Do nothing, no action is taken on PWMxB.

Reset type: SYSRSn

1-0TZAR/W0hTrip action on PWMxA

00: High-impedance (PWMxA = High-impedance state)
01: Force PWMxA to a high state
10: Force PWMxA to a low state
11: Do nothing, no action is taken on PWMxA.

Reset type: SYSRSn

15.12.3.30 TZCBCOSTFLAG Register (Offset = 58h) [Reset = 00000000h]

TZCBCOSTFLAG is shown in Figure 15-138 and described in Table 15-115.

Return to the Summary Table.

Trip zone CBCOST flag

Figure 15-138 TZCBCOSTFLAG Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
OST8OST7OST6OST5OST4OST3OST2OST1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVED
R-0-0h
76543210
CBC8CBC7CBC6CBC5CBC4CBC3CBC2CBC1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 15-115 TZCBCOSTFLAG Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR-00hReserved
23OST8R0hLatched Status Flag for OST TZ8 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ8.
1: Reading a 1 indicates a OST trip has occured by TZ8.

Reset type: SYSRSn

22OST7R0hLatched Status Flag for OST TZ7 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ7.
1: Reading a 1 indicates a OST trip has occured by TZ7.

Reset type: SYSRSn

21OST6R0hLatched Status Flag for OST TZ6 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ6.
1: Reading a 1 indicates a OST trip has occured by TZ6.

Reset type: SYSRSn

20OST5R0hLatched Status Flag for OST TZ5 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ5.
1: Reading a 1 indicates a OST trip has occured by TZ5.

Reset type: SYSRSn

19OST4R0hLatched Status Flag for OST TZ4 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ4.
1: Reading a 1 indicates a OST trip has occured by TZ4.

Reset type: SYSRSn

18OST3R0hLatched Status Flag for OST TZ3 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ3.
1: Reading a 1 indicates a OST trip has occured by TZ3.

Reset type: SYSRSn

17OST2R0hLatched Status Flag for OST TZ2 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ2.
1: Reading a 1 indicates a OST trip has occured by TZ2.

Reset type: SYSRSn

16OST1R0hLatched Status Flag for OST TZ1 Trip Latch

0: Reading a 0 indicates that no OST trip has occurred by TZ1.
1: Reading a 1 indicates a OST trip has occured by TZ1.

Reset type: SYSRSn

15-8RESERVEDR-00hReserved
7CBC8R0hLatched Status Flag for CBC TZ8 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ8.
1: Reading a 1 indicates a CBC trip has occured by TZ8.

Reset type: SYSRSn

6CBC7R0hLatched Status Flag for CBC TZ7 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ7.
1: Reading a 1 indicates a CBC trip has occured by TZ7.

Reset type: SYSRSn

5CBC6R0hLatched Status Flag for CBC TZ6 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ6.
1: Reading a 1 indicates a CBC trip has occured by TZ6.

Reset type: SYSRSn

4CBC5R0hLatched Status Flag for CBC TZ5 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ5.
1: Reading a 1 indicates a CBC trip has occured by TZ5.

Reset type: SYSRSn

3CBC4R0hLatched Status Flag for CBC TZ4 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ4.
1: Reading a 1 indicates a CBC trip has occured by TZ4.

Reset type: SYSRSn

2CBC3R0hLatched Status Flag for CBC TZ3 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ3.
1: Reading a 1 indicates a CBC trip has occured by TZ3.

Reset type: SYSRSn

1CBC2R0hLatched Status Flag for CBC TZ2 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ2.
1: Reading a 1 indicates a CBC trip has occured by TZ2.

Reset type: SYSRSn

0CBC1R0hLatched Status Flag for CBC TZ1 Trip Latch

0: Reading a 0 indicates that no CBC trip has occurred by TZ1.
1: Reading a 1 indicates a CBC trip has occured by TZ1.

Reset type: SYSRSn

15.12.3.31 TZCBCOSTCLR Register (Offset = 5Ah) [Reset = 00000000h]

TZCBCOSTCLR is shown in Figure 15-139 and described in Table 15-116.

Return to the Summary Table.

Trip zone CBCOST flag clear

Figure 15-139 TZCBCOSTCLR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
OST8OST7OST6OST5OST4OST3OST2OST1
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
RESERVED
R-0-0h
76543210
CBC8CBC7CBC6CBC5CBC4CBC3CBC2CBC1
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 15-116 TZCBCOSTCLR Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR-00hReserved
23OST8R-0/W1S0hClear OST TZ8 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST8] bit.

Reset type: SYSRSn

22OST7R-0/W1S0hClear OST TZ7 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST7] bit.

Reset type: SYSRSn

21OST6R-0/W1S0hClear OST TZ6 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST6] bit.

Reset type: SYSRSn

20OST5R-0/W1S0hClear OST TZ5 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST5] bit.

Reset type: SYSRSn

19OST4R-0/W1S0hClear OST TZ4 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST4] bit.

Reset type: SYSRSn

18OST3R-0/W1S0hClear OST TZ3 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST3] bit.

Reset type: SYSRSn

17OST2R-0/W1S0hClear OST TZ2 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST2] bit.

Reset type: SYSRSn

16OST1R-0/W1S0hClear OST TZ1 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[OST1] bit.

Reset type: SYSRSn

15-8RESERVEDR-00hReserved
7CBC8R-0/W1S0hClear CBC TZ8 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC8] bit.

Reset type: SYSRSn

6CBC7R-0/W1S0hClear CBC TZ7 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC7] bit.

Reset type: SYSRSn

5CBC6R-0/W1S0hClear CBC TZ6 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC6] bit.

Reset type: SYSRSn

4CBC5R-0/W1S0hClear CBC TZ5 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC5] bit.

Reset type: SYSRSn

3CBC4R-0/W1S0hClear CBC TZ4 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC4] bit.

Reset type: SYSRSn

2CBC3R-0/W1S0hClear CBC TZ3 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC3] bit.

Reset type: SYSRSn

1CBC2R-0/W1S0hClear CBC TZ2 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC2] bit.

Reset type: SYSRSn

0CBC1R-0/W1S0hClear CBC TZ1 Status Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCOSTFLAG[CBC1] bit.

Reset type: SYSRSn

15.12.3.32 DBCTL Register (Offset = 60h) [Reset = 00000000h]

DBCTL is shown in Figure 15-140 and described in Table 15-117.

Return to the Summary Table.

Dead band control register

Figure 15-140 DBCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDLOADREDMODELOADFEDMODE
R-0-0hR/W-0hR/W-0h
15141312111098
RESERVEDDEDB_MODE
R-0-0hR/W-0h
76543210
OUTSWAPIN_MODEPOLSELOUT_MODE
R/W-0hR/W-0hR/W-0hR/W-0h
Table 15-117 DBCTL Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR-00hReserved
19-18LOADREDMODER/W0hShadow to Active load of DBRED register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

17-16LOADFEDMODER/W0hShadow to Active load of DBFED register

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

15-9RESERVEDR-00hReserved
8DEDB_MODER/W0hDead Band Dual-Edge B Mode Control (S8 switch)

0: Rising edge delay applied to InA/InB as selected by S4 switch (IN-MODE bits) on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch (INMODE bits) on B signal path only.
1: Rising edge delay and falling edge delay applied to source selected by S4 switch (INMODE bits) and output to B signal path only. Note: When this bit is set to 1, user should always either set OUT_MODE bits such that Apath = InA OR OUTSWAP bits such that OutA=Bpath
otherwise, OutA will be invalid.

Reset type: SYSRSn

7-6OUTSWAPR/W0hDead Band Output Swap Control

Bit 7 controls the S6 switch and bit 6 controls the S7 switch.

00: OutA and OutB signals are as defined by OUT-MODE bits.
01: OutA = A-path as defined by OUT-MODE bits.
OutB = A-path as defined by OUT-MODE bits (rising edge delay or delay-bypassed A signal path).
10: OutA = B-path as defined by OUT-MODE bits (falling edge delay or delay-bypassed B signal path).
OutB = B-path as defined by OUT-MODE bits.
11: OutA = B-path as defined by OUT-MODE bits (falling edge delay or delay-bypassed B signal path).
OutB = A-path as defined by OUT-MODE bits (rising edge delay or delay-bypassed A signal path).

Reset type: SYSRSn

5-4IN_MODER/W0hDead-Band Input Mode Control

Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is PWMxA In is the source for both falling and rising-edge delays.

00: PWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
01: PWMxB In (from the action-qualifier) is the source for rising-edge delayed signal.
PWMxA In (from the action-qualifier) is the source for falling-edge delayed signal.
10: PWMxA In (from the action-qualifier) is the source for rising-edge delayed signal.
PWMxB In (from the action-qualifier) is the source for falling-edge delayed signal.
11: PWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed signal.

Reset type: SYSRSn

3-2POLSELR/W0hPolarity Select Control

Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter. These assume that DBCTL[OUT_MODE] = 1,1 and DBCTL[IN_MODE] = 0x0. Other enhanced modes are also possible, but not regarded as typical usage modes.

00: Active high (AH) mode. Neither PWMxA nor PWMxB is inverted (default).
01: Active low complementary (ALC) mode. PWMxA is inverted.
10: Active high complementary (AHC). PWMxB is inverted.
11: Active low (AL) mode. Both PWMxA and PWMxB are inverted.

Reset type: SYSRSn

1-0OUT_MODER/W0hDead-Band Output Mode Control

Bit 1 controls the S1 switch and bit 0 controls the S0 switch.

00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect.
01: Apath = InA (delay is by-passed for A signal path)
Bpath = FED (Falling Edge Delay in B signal path)
10: Apath = RED (Rising Edge Delay in A signal path)
Bpath = InB (delay is by-passed for B signal path)
11: DBM is fully enabled (i.e. both RED and FED active)

Reset type: SYSRSn

15.12.3.33 DBFED Register (Offset = 68h) [Reset = 00000000h]

DBFED is shown in Figure 15-141 and described in Table 15-118.

Return to the Summary Table.

Dead band fall edge delay

Figure 15-141 DBFED Register
313029282726252423222120191817161514131211109876543210
RESERVEDDBFED
R-0-0hR/W-0h
Table 15-118 DBFED Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR-00hReserved
13-0DBFEDR/W0hFalling Edge Delay Count

14-bit counter

Reset type: SYSRSn

15.12.3.34 DBRED Register (Offset = 6Ah) [Reset = 00000000h]

DBRED is shown in Figure 15-142 and described in Table 15-119.

Return to the Summary Table.

Dead band rise edge delay

Figure 15-142 DBRED Register
313029282726252423222120191817161514131211109876543210
RESERVEDDBRED
R-0-0hR/W-0h
Table 15-119 DBRED Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR-00hReserved
13-0DBREDR/W0hRising Edge Delay Count

14-bit counter

Reset type: SYSRSn

15.12.3.35 DBFEDS Register (Offset = 6Ch) [Reset = 00000000h]

DBFEDS is shown in Figure 15-143 and described in Table 15-120.

Return to the Summary Table.

Dead band fall edge delay shadow register

Figure 15-143 DBFEDS Register
313029282726252423222120191817161514131211109876543210
RESERVEDDBFEDS
R-0-0hR/W-0h
Table 15-120 DBFEDS Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR-00hReserved
13-0DBFEDSR/W0hDBFED Shadow Register

The value in the DBFEDS register is loaded into DBFED register when shadow to active load occurs.

Reset type: SYSRSn

15.12.3.36 DBREDS Register (Offset = 6Eh) [Reset = 00000000h]

DBREDS is shown in Figure 15-144 and described in Table 15-121.

Return to the Summary Table.

Dead band rise edge delay shadow register

Figure 15-144 DBREDS Register
313029282726252423222120191817161514131211109876543210
RESERVEDDBREDS
R-0-0hR/W-0h
Table 15-121 DBREDS Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR-00hReserved
13-0DBREDSR/W0hDBRED Shadow Register

The value in the DBREDS register is loaded into DBRED register when shadow to active load occurs.

Reset type: SYSRSn

15.12.3.37 GLDCTL Register (Offset = 78h) [Reset = 00000000h]

GLDCTL is shown in Figure 15-145 and described in Table 15-122.

Return to the Summary Table.

Global load control register

Figure 15-145 GLDCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDGLDMODERESERVEDOSHTMODEGLD
R-0-0hR/W-0hR-0-0hR/W-0hR/W-0h
Table 15-122 GLDCTL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5-4GLDMODER/W0hSelect global load event

00: CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: CTR = Zero or CTR = PRD
11: GLDOSHTCTL[GFRCLD] - Softwrae load

Reset type: SYSRSn

3-2RESERVEDR-00hReserved
1OSHTMODER/W0hGlobal load one-shot enable

0: Disable global load one-shot
1: Enable global load one-shot

Reset type: SYSRSn

0GLDR/W0hGlobal load enable

0: Disable global load
1: Enable global load

Reset type: SYSRSn

15.12.3.38 GLDOSHTCTL Register (Offset = 7Ah) [Reset = 00000000h]

GLDOSHTCTL is shown in Figure 15-146 and described in Table 15-123.

Return to the Summary Table.

Global load one shot control register

Figure 15-146 GLDOSHTCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDGFRCLDOSHTCLROSHTLD
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 15-123 GLDOSHTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR-00hReserved
2GFRCLDR-0/W1S0hForce Load Event in One Shot Mode

0: Writing of 0 will be ignored. Always reads back a 0.
1: Force load event. This bit is intended to be used for testing and/or software force loading of the events in global load mode.

Reset type: SYSRSn

1OSHTCLRR-0/W1S0hClear One Shot latch

0: Writing of 0 will be ignored. Always reads back a 0.
1: Turns the one shot latch condition OFF.

Reset type: SYSRSn

0OSHTLDR-0/W1S0hEnable Reload Event in One Shot Mode

0: Writing of 0 will be ignored. Always reads back a 0.
1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe, one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow one load strobe event to pass through and block further strobe events.

Reset type: SYSRSn

15.12.3.39 GLDOSHTSTS Register (Offset = 7Ch) [Reset = 00000000h]

GLDOSHTSTS is shown in Figure 15-147 and described in Table 15-124.

Return to the Summary Table.

Global load one shot status register

Figure 15-147 GLDOSHTSTS Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDOSHTLATCH
R-0-0hR-0h
Table 15-124 GLDOSHTSTS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0OSHTLATCHR0hOne shot latch output

0: one shot latch condition is OFF.
1: one shot latch condition is ON.

Reset type: SYSRSn

15.12.3.40 PWM1_CMPA Register (Offset = 80h) [Reset = 00000000h]

PWM1_CMPA is shown in Figure 15-148 and described in Table 15-125.

Return to the Summary Table.

PWM1 counter compare A register

Figure 15-148 PWM1_CMPA Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM1_CMPA
R-0-0hR/W-0h
Table 15-125 PWM1_CMPA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM1_CMPAR/W0hPWM1 Compare A register

The value in the PWM1_CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal, the PWM1 counter-compare module generates a 'time-base counter equal to CMP A' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the PWM1A or the PWM1B output depending on the configuration of the PWM1_AQCTLA and PWM1_AQCTLB registers

Shadowing of this register is enabled and disabled by the CMPCTL[PWM1_LOADAMODE] field. By default this register is shadowed.

Reset type: SYSRSn

15.12.3.41 PWM1_CMPAS Register (Offset = 82h) [Reset = 00000000h]

PWM1_CMPAS is shown in Figure 15-149 and described in Table 15-126.

Return to the Summary Table.

PWM1 counter compare A shadow register

Figure 15-149 PWM1_CMPAS Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM1_CMPAS
R-0-0hR/W-0h
Table 15-126 PWM1_CMPAS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM1_CMPASR/W0hPWM1 Compare A Shadow Register

The value in the PWM1_CMPAS register is loaded into PWM!_CMPA register when shadow to active load occurs.

Reset type: SYSRSn

15.12.3.42 PWM1_CMPB Register (Offset = 84h) [Reset = 00000000h]

PWM1_CMPB is shown in Figure 15-150 and described in Table 15-127.

Return to the Summary Table.

PWM1 counter compare B register

Figure 15-150 PWM1_CMPB Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM1_CMPB
R-0-0hR/W-0h
Table 15-127 PWM1_CMPB Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM1_CMPBR/W0hPWM1 Compare B register

The value in the PWM1_CMPB register is continuously compared to the time-base counter (TBCTR). When the values are equal, the PWM1 counter-compare module generates a 'time-base counter equal to CMP B' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the PWM1A or the PWM1B output depending on the configuration of the PWM1_AQCTLA and PWM1_AQCTLB registers

Shadowing of this register is enabled and disabled by the CMPCTL[PWM1_LOADBMODE] field. By default this register is shadowed.

Reset type: SYSRSn

15.12.3.43 PWM1_CMPBS Register (Offset = 86h) [Reset = 00000000h]

PWM1_CMPBS is shown in Figure 15-151 and described in Table 15-128.

Return to the Summary Table.

PWM1 counter compare B shadow register

Figure 15-151 PWM1_CMPBS Register
313029282726252423222120191817161514131211109876543210
RESERVEDPWM1_CMPBS
R-0-0hR/W-0h
Table 15-128 PWM1_CMPBS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0PWM1_CMPBSR/W0hPWM1 Compare B Shadow Register

The value in the PWM1 CMPBS register is loaded into PWM1 CMPB register when shadow to active load occurs.

Reset type: SYSRSn

15.12.3.44 PWM1_AQCTLA Register (Offset = 90h) [Reset = 00000000h]

PWM1_AQCTLA is shown in Figure 15-152 and described in Table 15-129.

Return to the Summary Table.

PWM1 action qualifier A register

Figure 15-152 PWM1_AQCTLA Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-129 PWM1_AQCTLA Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM1_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM1_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM1_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM1_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

15.12.3.45 PWM1_AQCTLAS Register (Offset = 92h) [Reset = 00000000h]

PWM1_AQCTLAS is shown in Figure 15-153 and described in Table 15-130.

Return to the Summary Table.

PWM1 action qualifier A shadow register

Figure 15-153 PWM1_AQCTLAS Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-130 PWM1_AQCTLAS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM1_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM1_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM1_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM1_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM1A output low.
10: Set: force PWM1A output high.
11: Toggle PWM1A output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

15.12.3.46 PWM1_AQCTLB Register (Offset = 94h) [Reset = 00000000h]

PWM1_AQCTLB is shown in Figure 15-154 and described in Table 15-131.

Return to the Summary Table.

PWM1 action qualifier B register

Figure 15-154 PWM1_AQCTLB Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-131 PWM1_AQCTLB Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM1_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM1_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM1_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM1_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

15.12.3.47 PWM1_AQCTLBS Register (Offset = 96h) [Reset = 00000000h]

PWM1_AQCTLBS is shown in Figure 15-155 and described in Table 15-132.

Return to the Summary Table.

PWM1 action qualifier B shadow register

Figure 15-155 PWM1_AQCTLBS Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDCBDCBUCADCAUPRDZRO
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 15-132 PWM1_AQCTLBS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = PWM1_CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = PWM1_CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = PWM1_CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = PWM1_CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

00: Do nothing (action disabled)
01: Clear: force PWM1B output low.
10: Set: force PWM1B output high.
11: Toggle PWM1B output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

15.12.3.48 PWM1_AQSFRC Register (Offset = 98h) [Reset = 00000000h]

PWM1_AQSFRC is shown in Figure 15-156 and described in Table 15-133.

Return to the Summary Table.

PWM1 action qualifier software force

Figure 15-156 PWM1_AQSFRC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDPWMBRESERVEDPWMA
R-0-0hR/W-0hR-0-0hR/W-0h
Table 15-133 PWM1_AQSFRC Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR-00hReserved
6-4PWMBR/W0hAction qualifier software force on PWMB

000: Does nothing (softwrae force disabled)
001: Forces a continuous low on output B
010: Forces a continuous high on output B
011: Does nothing (softwrae force disabled)
100: Does nothing (softwrae force disabled)
101: Clear (low) when PWM1_AQOTSFRC[PWMB] = '1'.
110: Set (high) when PWM1_AQOTSFRC[PWMB] = '1'.
111: Toggle (Low -> High, High -> Low) when PWM1_AQOTSFRC[PWMB] = '1'.

Reset type: SYSRSn

3RESERVEDR-00hReserved
2-0PWMAR/W0hAction qualifier software force on PWMA

000: Does nothing (softwrae force disabled)
001: Forces a continuous low on output A
010: Forces a continuous high on output A
011: Does nothing (softwrae force disabled)
100: Does nothing (softwrae force disabled)
101: Clear (low) when PWM1_AQOTSFRC[PWMA] = '1'.
110: Set (high) when PWM1_AQOTSFRC[PWMA] = '1'.
111: Toggle (Low -> High, High -> Low) when PWM1_AQOTSFRC[PWMA] = '1'.

Reset type: SYSRSn

15.12.3.49 PWM1_AQOTSFRC Register (Offset = 9Ah) [Reset = 00000000h]

PWM1_AQOTSFRC is shown in Figure 15-157 and described in Table 15-134.

Return to the Summary Table.

PWM1 action qualifier one time software force

Figure 15-157 PWM1_AQOTSFRC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDPWMBRESERVEDPWMA
R-0-0hR-0/W1S-0hR-0-0hR-0/W1S-0h
Table 15-134 PWM1_AQOTSFRC Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR-00hReserved
4PWMBR-0/W1S0hAction qualifier one time software force on PWMB

0: Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (i.e., a forced event is initiated.). This is a one-shot forced event. It can be overridden by another subsequent event on PWMB.
1: Initiates a single software forced event

Reset type: SYSRSn

3-1RESERVEDR-00hReserved
0PWMAR-0/W1S0hAction qualifier one time software force on PWMA

0: Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (i.e., a forced event is initiated.). This is a one-shot forced event. It can be overridden by another subsequent event on PWMA.
1: Initiates a single software forced event

Reset type: SYSRSn