SPRUJE5A June   2025  – August 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
      1. 1.3.1 External Power Supply or Accessory Requirements
    4. 1.4 Device Information
  7. 2Software
    1. 2.1 Software Description
    2. 2.2 Software Installation
      1. 2.2.1 Install SDK
      2. 2.2.2 Install Additional Software
        1. 2.2.2.1 Install Python
        2. 2.2.2.2 Install OpenSSL
    3. 2.3 Software Development
    4. 2.4 F29H85x LaunchPad Demo Program
    5. 2.5 Programming and Running Other Software on the F29H85x LaunchPad
  8. 3Hardware
    1. 3.1 Hardware Description
      1. 3.1.1 Functional Description and Connections
        1. 3.1.1.1  Microcontroller
        2. 3.1.1.2  PMIC
        3. 3.1.1.3  Power Domains
        4. 3.1.1.4  LEDs
        5. 3.1.1.5  Encoder Connectors
        6. 3.1.1.6  FSI
        7. 3.1.1.7  CAN
        8. 3.1.1.8  SENT
        9. 3.1.1.9  CLB
        10. 3.1.1.10 Boot Modes
        11. 3.1.1.11 BoosterPack Sites
        12. 3.1.1.12 Analog Voltage Reference
        13. 3.1.1.13 Differential ADC Header
        14. 3.1.1.14 Other Headers and Jumpers
          1. 3.1.1.14.1 XDS Isolation Block
          2. 3.1.1.14.2 BoosterPack Site 2 Power Isolation
          3. 3.1.1.14.3 Alternate Power
      2. 3.1.2 Debug Interface
        1. 3.1.2.1 XDS110 Debug Probe
        2. 3.1.2.2 XDS110 Output
        3. 3.1.2.3 Virtual COM Port
      3. 3.1.3 Alternate Routing
        1. 3.1.3.1 Overview
        2. 3.1.3.2 UART Routing
        3. 3.1.3.3 EQEP Routing
        4. 3.1.3.4 CAN Routing
        5. 3.1.3.5 FSI Routing
        6. 3.1.3.6 PWM DAC
      4. 3.1.4 Hardware Revisions
        1. 3.1.4.1 Revision A
  9. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
      1. 4.2.1 LAUNCHXL-F29H85X Board Dimensions
    3. 4.3 Bill of Materials (BOM)
  10. 5Frequently Asked Questions
  11. 6Additional Information
    1. 6.1 Trademarks
  12. 7References
    1. 7.1 Reference Documents
    2. 7.2 Other TI Components Used in This Design
  13. 8Revision History

3.1.1.9 CLB

The configurable logic block (CLB) is a collection of blocks that can be interconnected using software to implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is able to enhance existing peripherals through a set of interconnections, which provide a high level of connectivity to existing control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules (eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to be connected to other internal peripheral signals of the device or external GPIO pins. In this way, the CLB can be configured to perform small logical functions to augment device peripheral inputs and outputs. Through the CLB, functions that can otherwise be accomplished using external logic devices, such as FPGAs or CPLDs, can now be implemented inside the C2000 MCU.

For more information on the CLB, see the C2000™ Configurable Logic Block (CLB) training series video.