Unlike the ADC found on the F2802x/03x where a single ADC has two sample-and-hold (S/H) circuits, the F28E12x utilizes one ADC with a single S/H circuit. This allows the F28E12x to efficiently manage multiple analog signals for enhanced overall system throughput. The ADC module is implemented using a successive approximation type ADC with a resolution of 12 bits and it provides a throughput of 8MSPS.

Like the F2802x/03x, ADC triggering and conversion sequencing is managed by a series of start-of-conversion (SOCx) configuration registers. However, the round robin and high priority modes are implemented on the F28E12x devices. Also, the F28E12x has four flexible PIE interrupts rather than nine found on the F2802x/03x.

To further enhance the capabilities of the F28E12x ADC, the ADC module incorporates three post-processing blocks (PPB), and each PPB can be linked to any of the ADC result registers. The PPBs can be used for hardware oversampling, offset correction, calculating an error from a set-point, detecting a limit and zero-crossing, and capturing a trigger-to-sample delay:

• The oversampling mode allows the application to easily perform multiple back-to-back samples from a single trigger pulse.

  When used in conjunction with the aggregation options in the post-processing block, this mode enables oversampling and averaging.

• Offset correction can simultaneously remove an offset associated with an ADCIN channel that was possibly caused by external sensors or signal sources with zero-overhead, thereby saving processor cycles.
• Error calculation can automatically subtract out a computed error from a set-point or expected result register value, reducing the sample to output latency and software overhead.
• Limit and zero-crossing detection automatically performs a check against a high/low limit or zero-crossing and can generate a trip to the MCPWM and/or generate an interrupt. This lowers the sample to MCPWM latency and reduces software overhead. Also, it can trip the MCPWM based on an out-of-range ADC conversion without any CPU intervention, which is useful for safety conscious applications.
• Sample delay capture records the delay between when the SOCx is triggered and when it begins to be sampled. This can enable software techniques to be used for reducing the delay error.
• The 12-bit ADC modules in this device include a sample capacitor reset feature to help mitigate memory crosstalk.