SPRZ375L October   2012  – June 2020 F28M36H33B2 , F28M36H53B2 , F28M36P53C2 , F28M36P63C2

 

  1.   F28M36x Concerto MCUs Silicon Errata Silicon Revisions F, E, B, A, 0
    1. 1 Introduction
    2. 2 Device and Development Support Tool Nomenclature
    3. 3 Device Markings
    4. 4 Usage Notes and Known Design Exceptions to Functional Specifications
      1. 4.1 Usage Notes
        1. 4.1.1  PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
        2. 4.1.2  FPU32 and VCU Back-to-Back Memory Accesses
        3. 4.1.3  Caution While Using Nested Interrupts
        4. 4.1.4  PBIST: PBIST Memory Test Feature is Deprecated
        5. 4.1.5  HWBIST: Cortex-M3 HWBIST Feature is Deprecated
        6. 4.1.6  HWBIST: C28x HWBIST Feature Support is Restricted to TI-Supplied Software
        7. 4.1.7  Flash Tools: Device Revision Requires a Flash Tools Update
        8. 4.1.8  EPI: New Feature Addition to EPI Module
        9. 4.1.9  EPI: ALE Signal Polarity
        10. 4.1.10 EPI: CS0/CS1 Swap
      2. 4.2 Known Design Exceptions to Functional Specifications
    5. 5 Documentation Support
  2.   Trademarks
  3.   Revision History

4.1.8 EPI: New Feature Addition to EPI Module

Revision(s) Affected: A, B, E, F

In the EPI module, many new features have been added on silicon revisions A and onwards. New configuration registers have been added to enable new features. However, in some cases, new configuration bits (which were “Reserved” on the revision 0 silicon) have been added to existing registers, without breaking the compatibility with the revision 0 silicon. Users should refer to the "External Peripheral Interface (EPI)" chapter in the Concerto F28M36x Technical Reference Manual to make sure their existing EPI code (which works on the revision 0 silicon) is not changing the default value of the new configuration bits. Otherwise, the old code may not work on the new silicon.