Revision(s) Affected:0, A, B, C
The SDFM clock input (SDx_Cy) directly clocks the SDFM module when there is no GPIO input synchronization. Any glitches or ringing noise on the SDx_Cy input beyond VIH or VIL can corrupt the SDFM module, leading to unpredictable results.
SDFM GPIO Asynchronous Mode:
Special attention should be taken during board design to ensure a clean and noise-free signal that meets the SDFM timing requirements. Precautions such as series termination for ringing due to any impedance mismatch of the clock driver, and spacing of traces from other high-frequency signals are recommended.
SDFM GPIO Qualification (3-sample) Mode:
It is highly recommended that the SDFM GPIO qualification mode be used in noisy conditions. This mode provides additional protection by filtering both SDx_Cy and SDx_Dy inputs from system noise. Refer to the "SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window)" table in the TMS320F2837xD Dual-Core Microcontrollers Data Manual when using this option.
When a noise event occurs while using the GPIO Qualification mode, there may still be data disturbance, but it will be proportional to the duration of the noise event and typically filtered by the oversampling of the SDFM module. Below is a relative listing of each SDFM mode's sensitivity to data variation in the presence of severe system noise.