TIDT283 May   2022

 

  1.   Description
  2.   Features
  3.   Applications
  4. 1Test Prerequisites
    1. 1.1 Voltage and Current Requirements
    2. 1.2 Required Equipment
    3. 1.3 Test Setup
  5. 2Testing and Results
    1. 2.1 UCC14240 Power-Up Sequence
    2. 2.2 UCC14240 Output Ripple
    3. 2.3 Gate Waveforms
    4. 2.4 Analog Sense
    5. 2.5 DESAT, OC
    6. 2.6 Thermal Images

2.6 Thermal Images

The test conditions for the thermal images are:

24-V input, VDD = 18 V, VEE= –4 V

The load is UCC21732 switching a 0.1-μF capacitive load.

Figure 2-10 shows the thermals while switching a 100-nF load at 1 kHz, which is about 0.18-W power through UCC14240. This is calculated as the sum of the power to charge the gate, and the quiescent power of the gate driver:

Equation 1. P g d = F s w × C × V g s × V g s = 1   k H z × 100   n F × 22   V × 22   V = 48.4   m W
Equation 2. Pig=Vgs×Iq=22 V×4 mA=88 mW
Equation 3. P g d + P i q = 48.4   m W + 88   m W = 136   m W

Figure 2-11 shows the thermals while switching a 100-nF load at 35 kHz, which is about 1.5-W power through UCC14240. This is calculated as the sum of the power to charge the gate, and the quiescent power of the gate driver:

Equation 4. P g d = F s w × C × V g s × V g s = 35   k H z × 100   n F × 22   V × 22   V = 1.69   W
Equation 5. Pig=Vgs×Iq=22 V×4 mA=88 mW
Equation 6. Pgd+Piq=1.69 W+88 mW=1.778 W

The soak time in both cases was 15 minutes, with no forced airflow.

At light load, the UCC14240 temperature peaks at 41.4°C, while the UCC21732 peaks at 38.1°C. The layout of this board balances thermal performance and switch node are. Thermals can be improved by increasing the thermal plane area on the secondary side.

GUID-20220505-SS0I-QPMB-MH0D-HNJNT0JTXNBS-low.jpg Figure 2-10 Thermal Image of 100-nF Load at 1 kHz, 0.17-W Power Draw

At peak load the UCC14240 temperature peaks at 86.9°C, while the UCC21732 peaks at 80.5°C. The highest temperature on the board is the gate resistors, which is not related to the performance of the ICs, and could be improved by paralleling multiple gate resistors or reducing the gate resistance. The layout of this board balances thermal performance and switch node are. Thermals can be improved by increasing the thermal plane area on the secondary side.

GUID-20220505-SS0I-DBKS-HL5J-G8TNZMLK8CMR-low.jpg Figure 2-11 Thermal Image of 100-nF Load at 35 kHz, 1.5-W Power Draw