TIDUEZ3A April   2021  – June 2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 LMG342xR030
      2. 2.3.2 TMS320F28002x
      3. 2.3.3 OPA607
      4. 2.3.4 UCC21222
  8. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Test Procedures
      2. 3.3.2 Performance Data: Efficiency, iTHD, and Power Factor
      3. 3.3.3 Functional Waveforms
        1. 3.3.3.1 Current Sensing and Protection
        2. 3.3.3.2 Power Stage Startup and Input Waveforms
        3. 3.3.3.3 AC Drop Test
        4. 3.3.3.4 Surge Test
        5. 3.3.3.5 EMI Test
      4. 3.3.4 Thermal Test
      5. 3.3.5 GaN FET Switching Waveform
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 Support Resources
    4. 4.4 Trademarks
  10. 5About the Author
  11. 6Revision History

Design Considerations

The digital power design includes power stage and control stage. The power stage design in this design is similar to all other boost PFC designs, similar to the design process of the 1-kW, 80 Plus titanium, GaN CCM totem pole bridgeless PFC and half-bridge LLC reference design (TIDA-010062). Figure 2-2 shows the power stage design parameters.


GUID-20210309-CA0I-LML2-VRGL-L2TQLVNXR2QF-low.gif

Figure 2-2 Power Stage Design Parameters

The following key considerations apply to control stage design:

  • Input current sensing

    In totem-pole PFCs, most AC current sense uses isolated current sensor, such as a Hall sensor, isolated amplifier, and current transformer. In common sense, analog isolation is more challenging than digital isolation. For example, compared with a non-isolated amplifier, a Hall sensor and isolated amplifier have relatively low bandwidth and larger propagation delay. But, dealing with the PWM drive isolation is much easier. In this design, the ground of the MCU was changed to the middle point of the MOSFET leg. This small change allows use of the shunt resistor to sense the current with a non-isolated amplifier.

    The OPA607 op amp with 50-MHz GBW is selected, this high-speed amplifier helps on current loop control and overcurrent protection on the MOSFET. The input current sense ratio is set on 0.033 V/A, and the sense range is –48 A to +48 A.

  • DC link voltage sensing

    After the ground of the controller is set at the middle of the MOSFET leg, the DC link has a high common-mode voltage relative to the controller ground. This common-mode voltage must be well suppressed with a resistor divider, and the CMRR of the amplifier is used to eliminate this disturbance.

    One channel of the LM358B, CMRR 20 µV/V, is used to sense the DC link voltage with differential amplifying circuits. The DC link voltage sense ratio is set to 0.0072, and the sensing range is set to 0 V to approximately 462 V.

  • Input AC voltage sensing

    Because the AC line voltage is negative in a half cycle, the 0-V input must be offset to 1.65-V output. Another channel of the LM358B is used to sense the AC line voltage, which performs the scale and introduces 1.65-V offset at the same time. The AC voltage sensing ratio is set to 0.0037, and the sensing range is set to –471 V to +471 V.

  • Input OCP (overcurrent protection)

    Input OCP could be realized by the CMPSS module integrated in the C2000, but an extra hardware OCP for the MOSFET leg is redundant in this design. Because the input current is bidirectional, the protection needs a dual-channel comparator. This design uses the TLV3502 to set both direction current protection with hysteresis loop. The protection threshold is set at –48 A and +50 A, with hysteresis.

  • DC bus OVP (overvoltage protection)

    Because overvoltage of the DC bus is very dangerous and will cause damage to property, a hardware OVP is included in this reference. This is strongly recommended before the firmware OVP is verified functionally good. This hardware OVP is easily implemented with one channel of the LM358B, and the OVP threshold is set on 445 V with 15-V hysteresis.

  • GaN FET driving

    This design uses the LMG3422EVM-043 GaN half bridge EVM as the switching leg. The EVM board includes two isolator ISO7741s and two SN6505 isolated DC/DC, for both high-side and low-side GaN FET. So the GaN bridge can be directly driven by the MCU.

    Note: For the EVM board: LMG3422EVM-043 uses 5 V on the MCU side of the VCC of the ISO7741. This is functionally workable with 3.3-V MCU logic, but it needs to change to 3.3 V for matching on the logic level.

  • MOSFET driving

    Because the ground of the controller is set at the middle of the MOSFET leg, the low-side MOSFET has –400 V when the high-side MOSFET turns on, a functional isolated driver is required in this situiation. The UCC21225A with VLGA package can be used when PCB layout space is very limited, but in this design, the UCC21222 with SO-16 package is the most cost-effective choice. Both the UCC21222 and UCC21225A could realize interlock function using dead-time configuration.

  • Inrush protection

    All PFC stages need to deal with the inrush current during AC power on. A mechanical relay and a resistor or PTC are often used to perform the current limitation. But, when the current is greater than 16 A, relay becomes very bulky and hard to choose. So, in this design, inrush relay is replaced by a MOSFET with isolated drive. Because of the MOSFET body diode, it cannot block the current from source to drain, and to avoid this, it must use two back-to-back MOSFETs, the inrush MOSFET is placed on the DC link side.