TIDUEZ3A April   2021  – June 2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 LMG342xR030
      2. 2.3.2 TMS320F28002x
      3. 2.3.3 OPA607
      4. 2.3.4 UCC21222
  8. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Test Procedures
      2. 3.3.2 Performance Data: Efficiency, iTHD, and Power Factor
      3. 3.3.3 Functional Waveforms
        1. 3.3.3.1 Current Sensing and Protection
        2. 3.3.3.2 Power Stage Startup and Input Waveforms
        3. 3.3.3.3 AC Drop Test
        4. 3.3.3.4 Surge Test
        5. 3.3.3.5 EMI Test
      4. 3.3.4 Thermal Test
      5. 3.3.5 GaN FET Switching Waveform
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 Support Resources
    4. 4.4 Trademarks
  10. 5About the Author
  11. 6Revision History

UCC21222

The UCC21222 device is an isolated dual channel gate driver with programmable dead time. It is designed with 4-A peak-source and 6-A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.

The UCC21222 device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. Five-ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.

The input side is isolated from the two output drivers by a 3.0-kV RMS isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI).

Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include: Disable feature to shut down both outputs simultaneously when DIS is set high, integrated deglitch filter that rejects input transients shorter than 5-ns, and negative voltage handling for up to –2-V spikes for 200-ns on input and output pins. All supplies have UVLO protection.