TIDUEZ3A April   2021  – June 2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 LMG342xR030
      2. 2.3.2 TMS320F28002x
      3. 2.3.3 OPA607
      4. 2.3.4 UCC21222
  8. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Test Procedures
      2. 3.3.2 Performance Data: Efficiency, iTHD, and Power Factor
      3. 3.3.3 Functional Waveforms
        1. 3.3.3.1 Current Sensing and Protection
        2. 3.3.3.2 Power Stage Startup and Input Waveforms
        3. 3.3.3.3 AC Drop Test
        4. 3.3.3.4 Surge Test
        5. 3.3.3.5 EMI Test
      4. 3.3.4 Thermal Test
      5. 3.3.5 GaN FET Switching Waveform
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 Support Resources
    4. 4.4 Trademarks
  10. 5About the Author
  11. 6Revision History

Surge Test

A lighting surge test between ACL and ACN was performed on this design. Figure 3-14 shows the 3kV line to neutral surge voltage waveform when EUT is not connected.


GUID-20210309-CA0I-R0X6-1XW2-XSFWCFLLTGQM-low.png

Figure 3-14 Surge Voltage Waveform

With this surge waveform, the input current and the PFC choke current which is same with the current flow through GaN FET was tested. The result shows the surge current is fully bypassed by the inrush diodes clearly, and no risk to GaN FET (see Figure 3-15).


GUID-20210309-CA0I-K8BQ-VVGM-HRHS4VVHHVRK-low.png

Figure 3-15 GaN FET, Choke Current in Surge Test

The surge current flow through MOSFET is a threat. As the test waveform in Figure 3-16 shows, the current under 3-kV surge exceeded the maximum peak current specification of the MOSFET.


GUID-20210309-CA0I-VSWM-N5BK-MMDSGCNXQK9F-low.png

Figure 3-16 Surge Current Through MOSFET

Experiments show that the power stage is survived at the ±3-kV surge, but the MOSFET leg is broken at the the –4-kV surge. Figure 3-17 and Figure 3-18 illustrate the surge waveforms under ±3-kV, respectively.


GUID-20210309-CA0I-VFD7-PVZB-KNRQ9DVBNLKS-low.png

Figure 3-17 Surge Test at +3 kV 90 degrees

GUID-20210309-CA0I-4XJX-QNJC-BKTBS0300SS4-low.png

Figure 3-18 Surge Test at –3 kV 90 degree