TIDUF70A April   2024  – June 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 DAC39RF10-SEP
      2. 2.3.2 ADC12DJ5200-SEP
      3. 2.3.3 LMK04832-SEP
      4. 2.3.4 LMX2694-SEP
      5. 2.3.5 TPS7H4010-SEP
      6. 2.3.6 TPS7H1111-SEP
      7. 2.3.7 TPS7H1212-SEP
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
    4. 3.4 Test Procedure
    5. 3.5 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author
  12. 6Revision History

Description

This reference design is a discrete RF sampling transceiver supporting instantaneous signal bandwidths up to 5GHz. The design utilizes -SEP (Space Enhanced Plastic) grade, radiation tolerant active devices designed for space applications. The receiver uses the ADC12DJ5200-SEP ADC (Analog-to-Digital Converter). The transmitter uses the DAC39RF10-SEP DAC (Digital-to-Analog Converter). The data converters support a variety of different JESD modes facilitating 1 or 2 output channels operating up to the lower part of X-band. The receiver includes the TRF0208-SEP active balun for transforming single-ended input to differential output. The transmitter includes the TRF0108-SEP active balun for transforming the differential output to single ended. The clocking design resides on a daughter-board that plugs into the top of the primary data converter board. The clock card includes the LMK04832-SEP for generating and distributing low frequency clock and reference signals to the synthesizer, data converters, and FPGA. The LMX2694-SEP RF synthesizer provides the 10GHz sample clock to the DAC and the 5GHz sample clock to the ADC. The power design resides on a daughter card that plugs into the bottom of the board and handles power distribution to all of the active devices on the board.