TIDUF70A April   2024  – June 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 DAC39RF10-SEP
      2. 2.3.2 ADC12DJ5200-SEP
      3. 2.3.3 LMK04832-SEP
      4. 2.3.4 LMX2694-SEP
      5. 2.3.5 TPS7H4010-SEP
      6. 2.3.6 TPS7H1111-SEP
      7. 2.3.7 TPS7H1212-SEP
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
    4. 3.4 Test Procedure
    5. 3.5 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author
  12. 6Revision History

2.3.2 ADC12DJ5200-SEP

The ADC12DJ5200-SEP is a radiation tolerant RF sampling ADC. The ADC12DJ5200-SEP supports a sampling clock up to 5.2GHz. In the nominal operating mode the ADC samples up to 5.2GSPS and has two outputs. With dual edge sampling (DES), the effective sample clock doubles (by using both falling and rising edge of the clock). In this mode, the device has only one channel output but supports 5GHz of instantaneous bandwidth. The device operates in a variety of JESD204B/C modes with a wide frequency of operation up to 8GHz.