SNAS676D October   2015  – October 2017 LMK61A2-100M , LMK61A2-125M , LMK61A2-156M , LMK61A2-312M , LMK61A2-644M , LMK61E0-050M , LMK61E0-155M , LMK61E0-156M , LMK61E2-100M , LMK61E2-125M , LMK61E2-156M , LMK61E2-312M , LMK61I2-100M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  LVPECL Output Characteristics
    7. 6.7  LVDS Output Characteristics
    8. 6.8  HCSL Output Characteristics
    9. 6.9  OE Input Characteristics
    10. 6.10 Frequency Tolerance Characteristics
    11. 6.11 Power-On/Reset Characteristics (VDD)
    12. 6.12 PSRR Characteristics
    13. 6.13 PLL Clock Output Jitter Characteristics
    14. 6.14 Typical 156.25-MHz Output Phase Noise Characteristics
    15. 6.15 Additional Reliability and Qualification
    16. 6.16 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Ensuring Thermal Reliability
      2. 9.1.2 Best Practices for Signal Integrity
      3. 9.1.3 Recommended Solder Reflow Profile
  10. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • SIA|6
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Ultra-low Noise, High Performance
    • Jitter: 90 fs RMS Typical Fout > 100 MHz
    • PSRR: –70 dBc, Robust Supply Noise Immunity
  • Supported Output Format
    • LVPECL up to 1 GHz
    • LVDS up to 900 MHz
    • HCSL up to 400 MHz
  • Total Frequency Tolerance of ± 50 ppm (LMK61X2) and ± 25 ppm (LMK61X0)
  • 3.3-V Operating Voltage
  • Industrial Temperature Range (–40ºC to +85ºC)
  • 7 mm × 5 mm 6-Pin Package, Pin-Compatible With Industry Standard 7050 XO Package

2 Applications

  • High-Performance Replacement for Crystal, SAW, or Silicon-Based Oscillators
  • Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN
  • Test and Measurement
  • Medical Imaging
  • FPGA, Processor Attach

3 Description

The LMK61XX is an ultra-low jitter oscillator that generates a commonly used reference clock. The device is pre-programmed in factory to support any reference clock frequency; supported output formats are LVPECL up to 1 GHz, LVDS up to 900 MHz, and HCSL up to 400 MHz. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.

Device Information(1)

PART NUMBER OUTPUT FREQ (MHz) AND FORMAT TOTAL FREQ STABILITY (PPM) PACKAGE
LMK61A2-100M00 100 LVDS ± 50 6-pin QFM (7.0 mm x 5.0 mm)
LMK61A2-125M00 125 LVDS ± 50
LMK61A2-156M25 156.25 LVDS ± 50
LMK61A2-312M50 312.5 LVDS ± 50
LMK61A2-644M53 644.53125 LVDS ± 50
LMK61E0-050M00 50 LVPECL ± 25
LMK61E0-155M52 155.52 LVPECL ± 25
LMK61E0-156M25 156.25 LVPECL ± 25
LMK61E2-100M00 100 LVPECL ± 50
LMK61E2-125M00 125 LVPECL ± 50
LMK61E2-156M25 156.25 LVPECL ± 50
LMK61E2-312M50 312.5 LVPECL ± 50
LMK61I2-100M00 100 HCSL ± 50
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Pinout