SGUS034F February   2001  – June 2015 SMJ320VC33


  1. Features
  2. Description
  3. Revision History
  4. Description (continued)
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Recommended Operating Conditions
    3. 6.3  Electrical Characteristics
    4. 6.4  Phase-Locked Loop Characteristics Using EXTCLK or On-Chip Crystal Oscillator Timing Requirements
    5. 6.5  Circuit Parameters for On-Chip Crystal Oscillator Timing Requirements
    6. 6.6  Timing Requirements for EXTCLK, All Modes
    7. 6.7  Timing Requirements for Memory Read/Write for STRB
    8. 6.8  Timing Requirements for XF0 and XF1 when Executing LDFI or LDII
    9. 6.9  Timing Requirements for XF0 and XF1 when Executing SIGI
    10. 6.10 Timing Requirements for Changing XFx from Output to Input Mode
    11. 6.11 Timing Requirements for RESET
    12. 6.12 Timing Requirements for INT3 to INT0 Response
    13. 6.13 Timing Requirements for Serial Port
    14. 6.14 Timing Requirements for HOLD/HOLDA
    15. 6.15 Timing Requirements for Peripheral Pin General-Purpose I/O
    16. 6.16 Timing Requirements for Timer Pin
    17. 6.17 Timing Requirements for IEEE-1149.1 Test Access Port
    18. 6.18 Switching Characteristics for EXTCLK, All Modes
    19. 6.19 Switching Characteristics for Memory Read/Write for STRB
    20. 6.20 Switching Characteristics for XF0 and XF1 when Executing LDFI or LDII
    21. 6.21 Switching Characteristics for XF0 when Executing STFI or STII
    22. 6.22 Switching Characteristics for XF0 and XF1 when Executing SIGI
    23. 6.23 Switching Characteristics for Loading when XF is Configured as an Output
    24. 6.24 Switching Characteristics for Changing XFx from Output to Input Mode
    25. 6.25 Switching Characteristics for Changing XFx from an Input to an Output
    26. 6.26 Switching Characteristics for RESET
    27. 6.27 Switching Characteristics for IACK
    28. 6.28 Switching Characteristics for Serial Port
    29. 6.29 Switching Characteristics for HOLD/HOLDA
    30. 6.30 Switching Characteristics for Peripheral Pin General-Purpose I/O
    31. 6.31 Switching Characteristics for Timer Pin
    32. 6.32 Switching Characteristics for SHZ
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  JTAG Scan-Based Emulation Logic
      2. 8.2.2  Clock Generator
      3. 8.2.3  PLL and Clock Oscillator Control
      4. 8.2.4  PLL Isolation
      5. 8.2.5  Clock and PLL Considerations on Initialization
      6. 8.2.6  EDGEMODE
      7. 8.2.7  Reset Operation
      8. 8.2.8  PAGE0 to PAGE3 Select Lines
      9. 8.2.9  Using External Logic With the READY Pin
      10. 8.2.10 Posted Writes
      11. 8.2.11 Data Bus I/O Buffer
      12. 8.2.12 Bootloader Operation
      13. 8.2.13 JTAG Emulation
      14. 8.2.14 Designing a Target System Emulator Connector (14-Pin Header)
      15. 8.2.15 JTAG Emulator Cable Pod Logic
      16. 8.2.16 Reset Timing
      17. 8.2.17 Interrupt Response TIming
      18. 8.2.18 Interrupt-Acknowledge Timing
      19. 8.2.19 Data-Rate Timing Modes
      20. 8.2.20 HOLD Timing
      21. 8.2.21 General-Purpose I/O Timing
      22. 8.2.22 Peripheral Pin I/O Timing
      23. 8.2.23 Timer Pin Timing
    3. 8.3 Register Maps
  9. Power Supply Recommendations
    1. 9.1 Power Sequencing Considerations
  10. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Timing Parameter Symbology
      2. 10.2.2 Device and Development-Support Tool Nomenclature
    3. 10.3 Related Links
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information



  • HFG|164

1 Features

  • High-Performance Floating-Point Digital Signal Processor (DSP)
    • SMx320VC33-150
      • 13-ns Instruction Cycle Time
      • 150 Million Floating-Point Operations per Second (MFLOPS)
      • 75 Million Instructions per Second (MIPS)
  • 34K × 32-Bit (1.1-Mbit) On-Chip Words of Dual-Access Static Random-Access Memory (SRAM) Configured in 2 × 16K plus 2 × 1K Blocks to Improve Internal Performance
  • x5 Phase-Locked Loop (PLL) Clock Generator
  • Very-Low Power: <200 mW at 150 MFLOPS
  • 32-Bit High-Performance CPU
  • 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
  • Four Internally Decoded Page Strobes to Simplify Interface to I/O and Memory Devices
  • Boot-Program Loader
  • EDGEMODE Selectable External Interrupts
  • 32-Bit Instruction Word, 24-Bit Addresses
  • Eight Extended-Precision Registers
  • Fabricated Using the 0.18-μm (leff – Effective Gate Length) TImeline™ Technology by Texas Instruments
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG)
  • On-Chip Memory-Mapped Peripherals:
    • One Serial Port
    • Two 32-Bit Timers
    • Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation
  • 164-Pin Low-Profile Quad Flatpack (HFG Suffix)
  • 144-Pin Non-Hermetic Ceramic Ball Grid Array (CBGA) (GNM Suffix)
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Two Low-Power Modes
  • Two- and Three-Operand Instructions
  • Parallel Arithmetic/Logic Unit (ALU) and Multiplier Execution in a Single Cycle
  • Block-Repeat Capability
  • Zero-Overhead Loops With Single-Cycle Branches
  • Conditional Calls and Returns
  • Interlocked Instructions for Multiprocessing Support
  • Bus-Control Registers Configure Strobe-Control Wait-State Generation
  • 1.8-V (Core) and 3.3-V (I/O) Supply Voltages

2 Description

The SMx320VC33 DSP is a 32-bit, floating-point processor manufactured in 0.18-μm four-level-metal CMOS (TImeline) technology. The SMx320VC33 is part of the SM320C3x™ generation of DSPs from Texas Instruments.

The SM320C3x internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 150 MFLOPS. The SMx320VC33 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

The SMx320VC33 can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. These features result in high performance and ease of use. General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure.

The SM320C3x supports a wide variety of system applications from host processor to dedicated coprocessor. High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

Device Information(1)

SM320VC33 CFP (164) 12.00 mm × 12.00 mm
SMJ320VC33 CFP (164) 29.09 mm × 29.09 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

3 Revision History

Changes from E Revision (October 2002) to F Revision

4 Description (continued)

The SM/SMJ320VC33 is a superset of the TMS320C31. Designers now have an additional 1Mb of on-chip SRAM, a maximum throughput of 150 MFLOPS, and several I/O enhancements that allow easy upgrades to current systems or creation of new baselines. This data sheet provides information required to fully use the new features of the SM/SMJ320VC33 device. For general TMS320C3x architecture and programming information, see the TMS320C3x User’s Guide (SPRU031).

The SMx320VC33 device is packaged in 164-pin low-profile quad flatpacks (HFG suffix) and in 144-ball fine pitch ball grid arrays (GNL and GNM suffix).