JAJSMF0B July   2021  – February 2024 LMX1204

PRODUCTION DATA  

1.   1
2. 1 特長
3. 2 アプリケーション
4. 3 概要
5. 4 Pin Configuration and Functions
6. 5 Specifications
   1. 5.1 Absolute Maximum Ratings
   2. 5.2 ESD Ratings
   3. 5.3 Recommended Operating Conditions
   4. 5.4 Thermal Information
   5. 5.5 Electrical Characteristics
   6. 5.6 Timing Requirements
   7. 5.7 Timing Diagram
   8. 5.8 Typical Characteristics
7. 6 Detailed Description
   1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
   2. 6.2 Functional Block Diagram
   3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
         1. 6.3.3.1 Clock Output Buffers
         2. 6.3.3.2 Clock MUX
         3. 6.3.3.3 Clock Divider
         4. 6.3.3.4 Clock Multiplier and Filter Modes
            1. 6.3.3.4.1 General Information About the Clock Multiplier
            2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
               1. 6.3.3.4.2.1 State Machine Clock
            3. 6.3.3.4.3 Calibration for the Clock Multiplier
            4. 6.3.3.4.4 Using the x1 Clock Multiplier as a Filter
            5. 6.3.3.4.5 Lock Detect for the Clock Multiplier
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
         1. 6.3.5.1 LOGICLK Output Format
         2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
         1. 6.3.6.1 SYSREF Output Buffers
            1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
            2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
         2. 6.3.6.2 SYSREF Frequency and Delay Generation
         3. 6.3.6.3 SYSREFREQ pins and SYSREFREQ_SPI Field
            1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
            2. 6.3.6.3.2 SYSREFREQ Windowing Feature
               1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
               2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)
      7. 6.3.7 SYNC Feature
   4. 6.4 Device Functional Modes
8. 7 Register Map
   1. 7.1 LMX1204 Registers
9. 8 Application and Implementation
   1. 8.1 Application Information
      1. 8.1.1 SYSREFREQ Input Configuration
      2. 8.1.2 Reducing SYSREF Common Mode Voltages
      3. 8.1.3 Current Consumption
      4. 8.1.4 Treatment of Unused Pins
   2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
   3. 8.3 Power Supply Recommendations
   4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
       1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
11. 10Revision History
12. 11Mechanical, Packaging, and Orderable Information

LMX1204 低ノイズ、高周波 JESD バッファ / 逓倍器 / 分周器

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