DLPU100B May   2020  – June 2024 DLP2021-Q1 , DLP3021-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Purpose and Scope
  5. 2FPGA Pin Configuration and Functions
    1. 2.1 DMD Interface
    2. 2.2 Light Control
    3. 2.3 Communication
    4. 2.4 Support
    5. 2.5 FPGA Dedicated Pins
    6. 2.6 Power and Ground
    7. 2.7 Unused Pins
  6. 3Specifications
    1. 3.1 Recommended Operating Conditions
    2. 3.2 FPGA Power Consumption
    3. 3.3 Host SPI Interface Timing
    4. 3.4 Power Supply and Reset Timing
      1. 3.4.1 Power-Up Timing
      2. 3.4.2 Power-Down Timing
      3. 3.4.3 Brownout Detection
    5. 3.5 DMD Interface Timing
    6. 3.6 Flash Memory Interface Timing
    7. 3.7 Reference Clock Timing
    8. 3.8 I2C Interface Timing
  7. 4Feature Descriptions
    1. 4.1 Video Control
      1. 4.1.1 Video Options
      2. 4.1.2 Example 1: Display a Static Image
      3. 4.1.3 Example 2: Display 1 Video Repeatedly
      4. 4.1.4 Example 3: Display Two Videos Then Stop
      5. 4.1.5 Example 4: Display a Video Once and Then Display an Image Forever
      6. 4.1.6 Example 5: Display 3+ Videos/Images Seamlessly
    2. 4.2 Temperature Measurements
    3. 4.3 PWM Outputs
    4. 4.4 Host IRQ Interrupt Signal
    5. 4.5 Video and Image Compression
  8. 5Layout
  9. 6Host Command Protocol
    1. 6.1 SPI Specifications
    2. 6.2 SPI Write Command
    3. 6.3 SPI Read Command
  10. 7FPGA Register Definitions
  11. 8Revision History

3.4.1 Power-Up Timing

Table 3-4 specifies the configuration and initialization timing during FPGA start-up. After Host_irq gets set high, the FPGA is configured and ready to receive commands on the SPI interface. However, the first commands will not be executed for an additional 10 ms.

Table 3-4 Power-up Timing Specifications
MIN NOM MAX UNIT
tinit(2) FPGA configuration initialization. 1.8V power to DONE rising edge 230 ms
toez DONE rising edge to DMD RESET OEZ low 8.5 ms
tirq(3) RESET OEZ low to HOST IRQ high 1.15 ms
tramp(1) Ramp time for each power supply: 1.0V, 1.8V, and 3.3V (GND to 90% reference points) 0.2 50 ms
(1) Value is based on FPGA documentation available at the time of writing. As primary source specification, see the device-specific FPGA data sheet.
(2) INITZ should be pulled up to 1.8V for shortest start-up time. If INITZ rising edge is delayed then the configuration will be delayed.
(3) HOST IRQ ready bit will indicate that the FPGA is ready for SPI communication from a host. This bit must be set in the interrupt enable mask in order for this condition to set HOST IRQ high at startup. The interrupt enable mask can be automatically configured on startup from the default configuration.
DLP3021-Q1 Power-up Timing Diagram Figure 3-2 Power-up Timing Diagram