SBAA415 April   2020 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1

 

  1.   Multiple PCM6xx0 Devices With Shared TDM and I2C Bus
    1.     Trademarks
    2. 1 Introduction
    3. 2 Sharing the Control Bus
    4. 3 Sharing the Audio Bus
      1. 3.1 ASI Configuration for Shared TDM
      2. 3.2 ASI Configuration for Daisy Chain TDM
    5. 4 Configuring PurePath Console for Multiple PCM6xx0 EVMs
      1. 4.1 Changing the Default I2C Address of the PCM6xx0 EVM
      2. 4.2 Launching PurePath Console With Multiple Devices
  2.   A PurePath Console I2C Scripts
    1.     A.1 PCM6xx0 I2C Scripts for Shared TDM
    2.     A.2 PCM6xx0 I2C Scripts for Daisy Chain TDM

A.2 PCM6xx0 I2C Scripts for Daisy Chain TDM

The following I2C scripts sets four devices for Daisy-Chain TDM mode, after devices are reset:

# Key: w NN YY ZZ ==> write to I2C address 0xNN, to register 0xYY, data 0xZZ # # ==> comment delimiter # # I2C programming script for four devices in daisy chain TDM mode # U4(SDOUT) -> (GPIO1) U3 (SDOUT) -> (GPIO1) U2 (SDOUT) -> (GPIO1) U1 (SDOUT) -> Host Processor # ######################################################################### # Power-up Sequence: # Power up IOVDD and AVDD power supplies keeping SHDNZ pin voltage LOW # Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range. # Release SHDNZ to HIGH. # Wait for 1ms. ######################################################################### # Wake-up devices w 90 02 81 # Wake-up Device U1 w 91 02 81 # Wake-up Device U2 w 92 02 81 # Wake-up Device U3 w 93 02 81 # Wake-up Device U4 d 10 # 10 ms delay # Program Device A (U1) w 90 00 00 # Set Device A page register to Page 0 w 90 07 31 # ASI Format TDM with 32-bit word length, default FSYNC and BCLK polarity, # default TX edge, Hi-Z for unused cycles w 90 08 A0 # ASI transmit LSB for 1st half cycle, Hi-Z for second half cycle, # bus keeper always enabled w 90 09 80 # ASI to daisy chain connection with bus error detection and # auto resume after bus error recovery w 90 21 B0 # GPIO1 input as ASI input for daisy chain w 90 0B 00 # ASI primary output (SDOUT) with CH1 assigned to slot 0 w 90 0C 01 # ASI primary output (SDOUT) with CH2 assigned to slot 1 w 90 0D 02 # ASI primary output (SDOUT) with CH3 assigned to slot 2 w 90 0E 03 # ASI primary output (SDOUT) with CH4 assigned to slot 3 w 90 73 F0 # Enable Ch1-4 of Device A w 90 74 F0 # Enable Ch1-4 ASI output of Device A # Program Device B (U2) w 91 00 00 # Set Device page register to Page 0 w 91 07 31 # ASI Format TDM with 32-bit word length, default FSYNC and BCLK polarity, # default TX edge, Hi-Z for unused cycles w 91 08 80 # ASI transmit LSB for 1st half cycle, Hi-Z for second half cycle, # bus keeper disabled w 91 09 80 # ASI to daisy chain connection with bus error detection and # auto resume after bus error recovery w 91 21 B0 # GPIO1 input as ASI input for daisy chain w 91 0B 04 # ASI primary output (SDOUT) with CH1 assigned to slot 4 w 91 0C 05 # ASI primary output (SDOUT) with CH2 assigned to slot 5 w 91 0D 06 # ASI primary output (SDOUT) with CH3 assigned to slot 6 w 91 0E 07 # ASI primary output (SDOUT) with CH4 assigned to slot 7 w 91 73 F0 # Enable Ch1-4 of Device B w 91 74 F0 # Enable Ch1-4 ASI output of Device B # Program Device C (U3) w 92 00 00 # Set Device page register to Page 0 w 92 07 31 # ASI Format TDM with 32-bit word length, default FSYNC and BCLK polarity, # default TX edge, Hi-Z for unused cycles w 92 08 80 # ASI transmit LSB for 1st half cycle, Hi-Z for second half cycle, # bus keeper disabled w 92 09 80 # ASI to daisy chain connection with bus error detection and # auto resume after bus error recovery w 92 21 B0 # GPIO1 input as ASI input for daisy chain w 92 0B 08 # ASI primary output (SDOUT) with CH1 assigned to slot 8 w 92 0C 09 # ASI primary output (SDOUT) with CH2 assigned to slot 9 w 92 0D 0A # ASI primary output (SDOUT) with CH3 assigned to slot 10 w 92 0E 0B # ASI primary output (SDOUT) with CH4 assigned to slot 11 w 92 73 F0 # Enable Ch1-4 of Device C w 92 74 F0 # Enable Ch1-4 ASI output of Device C # Program Device D (U4) w 93 00 00 # Set Device page register to Page 0 w 93 07 31 # ASI Format TDM with 32-bit word length, default FSYNC and BCLK polarity, # default TX edge, Hi-Z for unused cycles w 93 08 80 # ASI transmit LSB for 1st half cycle, Hi-Z for second half cycle, # bus keeper disabled w 93 0B 0C # ASI primary output (SDOUT) with CH1 assigned to slot 12 w 93 0C 0D # ASI primary output (SDOUT) with CH2 assigned to slot 13 w 93 0D 0E # ASI primary output (SDOUT) with CH3 assigned to slot 14 w 93 0E 0F # ASI primary output (SDOUT) with CH4 assigned to slot 15 w 93 73 F0 # Enable Ch1-4 of Device D w 93 74 F0 # Enable Ch1-4 ASI output of Device D # Power-up Devices A, B, C, & D w 90 75 60 # Power up ADC and PLL of Device A w 91 75 60 # Power up ADC and PLL of Device B w 92 75 60 # Power up ADC and PLL of Device C w 93 75 60 # Power up ADC and PLL of Device D