8 Example

The DRE default parameters work well for most applications. The default DRE trigger threshold is -54 dB. This provides sufficient headroom for the DRE to react in a timely manner to a sudden loud signal. Increasing the DRE trigger threshold improves the small-signal performance, but it decreases the headroom available before switching to an attack cycle. This can be mitigated by decreasing the attack time. This section shows an example where a higher DRE trigger threshold is set and time constants adjusted to make the DRE respond faster.

• Target Level = -54 dB
• Maximum Gain = 24 dB
• Attack Time = 0.01 ms
• Release Time = 20 ms
• Attack Hold = 0.0417 ms
• Release Hold = 20 ms
• Attack Hysteresis = 1 dB
• Release Hysteresis = 3 dB

# Key: w 9C XX YY ==> write to I2C address 0x9c, to register 0xXX, data 0xYY
#               # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are 
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Differential 2-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies 
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Wait for 1ms.
#
w 9C 00 00 # Goto Page 0
w 9C 02 81 # Exit Sleep mode
d 10       # Wait for 16 ms
w 9C 01 01 # Reset
w 9C 6C 44 # Enable DRE in DSP_CFG1 and Override DRE parameters with user values
w 9C 3C 01 # Select DRE on Ch. 1 using CH1_CFG0
w 9C 41 01 # Select DRE on Ch. 2 using CH2_CFG0
w 9C 6D 4B # DRE LVL = -36 dB, DRE GAIN = 24 dB
w 9C 00 05          # Goto Page 5
w 9C 7C 7F B5 16 50 # DRE Release Time Alpha 
w 9C 00 05          # Goto Page 6
w 9C 08 00 4A E9 B0 # DRE Release Time Beta  
w 9C 0C 01 50 DB 39 # DRE Attack Time Alpha 
w 9C 10 7E B5 16 50 # DRE Attack Time Beta 
w 9C 18 00 00 02 00 # DRE Attack Debounce 
w 9C 1C 00 04 B0 00 # DRE Release Debounce 
w 9C 3C 00 00 01 00 # DRE Attack Hysteresis 
w 9C 34 00 00 03 00 # DRE Release Hysteresis
 
w 9C 00 00 # Goto Page 0
w 9C 07 30 # TDM Mode with 32 Bits/Channel
w 9C 73 c0 # Enable Ch.1 - Ch.2
w 9C 74 f0 # Enable ASI Output channels
w 9C 75 e0 # Power up ADC

To enable the DRC algorithm instead of DRE algorithm with the same parameter set as above, set DSP_CFG1 (Page 0, Register 0x6c) with a value 0x46 (instead of 0x44 for DRE).