SBAA532A February   2022  – March 2024 ADS1119 , ADS1120 , ADS1120-Q1 , ADS112C04 , ADS112U04 , ADS1130 , ADS1131 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1158 , ADS1219 , ADS1220 , ADS122C04 , ADS122U04 , ADS1230 , ADS1231 , ADS1232 , ADS1234 , ADS1235 , ADS1235-Q1 , ADS124S06 , ADS124S08 , ADS1250 , ADS1251 , ADS1252 , ADS1253 , ADS1254 , ADS1255 , ADS1256 , ADS1257 , ADS1258 , ADS1258-EP , ADS1259 , ADS1259-Q1 , ADS125H01 , ADS125H02 , ADS1260 , ADS1260-Q1 , ADS1261 , ADS1261-Q1 , ADS1262 , ADS1263 , ADS127L01 , ADS130E08 , ADS131A02 , ADS131A04 , ADS131E04 , ADS131E06 , ADS131E08 , ADS131E08S , ADS131M02 , ADS131M03 , ADS131M04 , ADS131M06 , ADS131M08

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Bridge Overview
  5. 2Bridge Construction
    1. 2.1 Active Elements in Bridge Topologies
      1. 2.1.1 Bridge With One Active Element
        1. 2.1.1.1 Reducing Non-Linearity in a Bridge With One Active Element Using Current Excitation
      2. 2.1.2 Bridge With Two Active Elements in Opposite Branches
        1. 2.1.2.1 Eliminating Non-Linearity in a Bridge With Two Active Elements in Opposite Branches Using Current Excitation
      3. 2.1.3 Bridge With Two Active Elements in the Same Branch
      4. 2.1.4 Bridge With Four Active Elements
    2. 2.2 Strain Gauge and Bridge Construction
  6. 3Bridge Connections
    1. 3.1 Ratiometric Measurements
    2. 3.2 Four-Wire Bridge
    3. 3.3 Six-Wire Bridge
  7. 4Electrical Characteristics of Bridge Measurements
    1. 4.1 Bridge Sensitivity
    2. 4.2 Bridge Resistance
    3. 4.3 Output Common-Mode Voltage
    4. 4.4 Offset Voltage
    5. 4.5 Full-Scale Error
    6. 4.6 Non-Linearity Error and Hysteresis
    7. 4.7 Drift
    8. 4.8 Creep and Creep Recovery
  8. 5Signal Chain Design Considerations
    1. 5.1 Amplification
      1. 5.1.1 Instrumentation Amplifier
        1. 5.1.1.1 INA Architecture and Operation
        2. 5.1.1.2 INA Error Sources
      2. 5.1.2 Integrated PGA
        1. 5.1.2.1 Integrated PGA Architecture and Operation
        2. 5.1.2.2 Benefits of Using an Integrated PGA
    2. 5.2 Noise
      1. 5.2.1 Noise in an ADC Data Sheet
      2. 5.2.2 Calculating NFC for a Bridge Measurement System
    3. 5.3 Channel Scan Time and Signal Bandwidth
      1. 5.3.1 Noise Performance
      2. 5.3.2 ADC Conversion Latency
      3. 5.3.3 Digital Filter Frequency Response
    4. 5.4 AC Excitation
    5. 5.5 Calibration
      1. 5.5.1 Offset Calibration
      2. 5.5.2 Gain Calibration
      3. 5.5.3 Calibration Example
  9. 6Bridge Measurement Circuits
    1. 6.1 Four-Wire Resistive Bridge Measurement with a Ratiometric Reference and a Unipolar, Low-Voltage (≤5 V) Excitation Source
      1. 6.1.1 Schematic
      2. 6.1.2 Pros and Cons
      3. 6.1.3 Parameters and Variables
      4. 6.1.4 Design Notes
      5. 6.1.5 Measurement Conversion
      6. 6.1.6 Generic Register Settings
    2. 6.2 Six-Wire Resistive Bridge Measurement With a Ratiometric Reference and a Unipolar, Low-Voltage (≤ 5 V) Excitation Source
      1. 6.2.1 Schematic
      2. 6.2.2 Pros and Cons
      3. 6.2.3 Parameters and Variables
      4. 6.2.4 Design Notes
      5. 6.2.5 Measurement Conversion
      6. 6.2.6 Generic Register Settings
    3. 6.3 Four-Wire Resistive Bridge Measurement With a Pseudo-Ratiometric Reference and a Unipolar, High-Voltage (> 5 V) Excitation Source
      1. 6.3.1 Schematic
      2. 6.3.2 Pros and Cons
      3. 6.3.3 Parameters and Variables
      4. 6.3.4 Design Notes
      5. 6.3.5 Measurement Conversion
      6. 6.3.6 Generic Register Settings
    4. 6.4 Four-Wire Resistive Bridge Measurement with a Pseudo-Ratiometric Reference and Asymmetric, High-Voltage (> 5 V) Excitation Source
      1. 6.4.1 Schematic
      2. 6.4.2 Pros and Cons
      3. 6.4.3 Parameters and Variables
      4. 6.4.4 Design Notes
      5. 6.4.5 Measurement Conversion
      6. 6.4.6 Generic Register Settings
    5. 6.5 Four-Wire Resistive Bridge Measurement With a Ratiometric Reference and Current Excitation
      1. 6.5.1 Schematic
      2. 6.5.2 Pros and Cons
      3. 6.5.3 Parameters and Variables
      4. 6.5.4 Design Notes
      5. 6.5.5 Measurement Conversion
      6. 6.5.6 Generic Register Settings
    6. 6.6 Measuring Multiple Four-Wire Resistive Bridges in Series with a Pseudo-Ratiometric Reference and a Unipolar, Low-Voltage (≤5V) Excitation Source
      1. 6.6.1 Schematic
      2. 6.6.2 Pros and Cons
      3. 6.6.3 Parameters and Variables
      4. 6.6.4 Design Notes
      5. 6.6.5 Measurement Conversion
      6. 6.6.6 Generic Register Settings
    7. 6.7 Measuring Multiple Four-Wire Resistive Bridges in Parallel Using a Single-Channel ADC With a Ratiometric Reference and a Unipolar, Low-Voltage (≤ 5 V) Excitation Source
      1. 6.7.1 Schematic
      2. 6.7.2 Pros and Cons
      3. 6.7.3 Parameters and Variables
      4. 6.7.4 Design Notes
      5. 6.7.5 Measurement Conversion
      6. 6.7.6 Generic Register Settings
    8. 6.8 Measuring Multiple Four-Wire Resistive Bridges in Parallel Using a Multichannel ADC With a Ratiometric Reference and a Unipolar, Low-Voltage (≤ 5 V) Excitation Source
      1. 6.8.1 Schematic
      2. 6.8.2 Pros and Cons
      3. 6.8.3 Parameters and Variables
      4. 6.8.4 Design Notes
      5. 6.8.5 Measurement Conversion
      6. 6.8.6 Generic Register Settings
  10. 7Summary
  11. 8Revision History

5.3 Channel Scan Time and Signal Bandwidth

In addition to low noise, bridge measurement systems often have channel scan time or input signal bandwidth requirements that can be affected by the ADC architecture. These applications typically use precision delta-sigma (ΔΣ) ADCs because they can offer resolution up to 32 bits and integrated PGAs. Precision ΔΣ ADCs use an oversampling topology where the input signal is sampled at a high frequency and converted to a digital bitstream by the ΔΣ ADC modulator. This bitstream is then filtered and decimated by the oversampling ratio (OSR) in the digital domain to yield a low-noise conversion result at the respective ODR.

The output noise depends on the OSR, where a larger OSR (or lower ODR) results in more data collected over a longer period of time and therefore lower noise. However, this also leads to extended ADC conversion latency and lower input signal bandwidth, though it may be possible to filter out line-cycle noise at lower data rates. The following subsections discuss these topics in more detail.