SBAA535A March   2022  – March 2024 ADC128D818 , ADS1000 , ADS1000-Q1 , ADS1013 , ADS1013-Q1 , ADS1014 , ADS1014-Q1 , ADS1015 , ADS1015-Q1 , ADS1018 , ADS1018-Q1 , ADS1100 , ADS1110 , ADS1112 , ADS1113 , ADS1113-Q1 , ADS1114 , ADS1114-Q1 , ADS1115 , ADS1115-Q1 , ADS1118 , ADS1118-Q1 , ADS1119 , ADS1120 , ADS1120-Q1 , ADS112C04 , ADS112U04 , ADS1130 , ADS1131 , ADS1146 , ADS1147 , ADS1148 , ADS1148-Q1 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1158 , ADS1216 , ADS1217 , ADS1218 , ADS1219 , ADS1220 , ADS122C04 , ADS122U04 , ADS1230 , ADS1231 , ADS1232 , ADS1234 , ADS1235 , ADS1235-Q1 , ADS1243-HT , ADS1246 , ADS1247 , ADS1248 , ADS124S06 , ADS124S08 , ADS1250 , ADS1251 , ADS1252 , ADS1253 , ADS1254 , ADS1255 , ADS1256 , ADS1257 , ADS1258 , ADS1258-EP , ADS1259 , ADS1259-Q1 , ADS125H01 , ADS125H02 , ADS1260 , ADS1260-Q1 , ADS1261 , ADS1261-Q1 , ADS1262 , ADS1263 , ADS127L01 , ADS1281 , ADS1282 , ADS1282-SP , ADS1283 , ADS1284 , ADS1287 , ADS1291 , LMP90080-Q1 , LMP90100 , TLA2021 , TLA2022 , TLA2024

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Data Sheet Timing and Nomenclature
  6. 3 What Causes Conversion Latency in a Delta-Sigma ADC?
  7. 4 Digital Filter Operation and Behavior
    1.     8
    2.     9
    3. 4.1 Unsettled Data Due to an ADC Operation
  8. 5 ADC Features and Modes that Affect Conversion Latency
    1. 5.1 First Conversion Versus Second and Subsequent Conversion Latency
    2. 5.2 Conversion Mode
    3. 5.3 Programmable Delay
    4. 5.4 ADC Overhead Time
    5. 5.5 Clock Frequency
    6. 5.6 Chopping
  9. 6 Analog Settling
  10. 7 Important Takeaways
  11. 8 Cycle Time Calculation Examples
    1. 8.1 Example #1: Using the ADS124S08
    2. 8.2 Example #2: Changing the Conversion Mode
    3. 8.3 Example #3: Changing the Filter Type
    4. 8.4 Example #4: Changing the Clock Frequency
    5. 8.5 Example #5: Enabling Chop and Reducing the Number of Conversions per Channel
    6. 8.6 Example #6: Scanning Two Channels With Different System Parameters
    7. 8.7 Example #7: Using the ADS1261
    8. 8.8 Example #8: Changing Multiple Parameters Using the ADS1261
  12. 9 Summary
  13. 10Revision History

4.1 Unsettled Data Due to an ADC Operation

An ADC operation such as a multiplexer change or a conversion start is similar to an applied step input and its effect on the digital filter. For example, changing from a channel with a –FS input to a channel with a +FS input mimics the step voltage that is applied immediately after conversion period N completes in Figure 4-2. When this occurs, does the user need to identify this action and manually discard these conversion results until settled data is available, similar to a step input?

Fortunately, one key difference between a multiplexer change and a step input is that many ADCs have provisions to automatically identify an ADC operation that can lead to unsettled data. The ADC then waits until the data is settled to indicate a new conversion result is ready. As an example of this behavior, the ADS124S08, a 24-bit, 4-kSPS, 12-channel delta-sigma ADC, automatically restarts the digital filter when certain register settings are changed – including the INPMUX register – or when a new conversion is triggered. Figure 4-7 shows how the ADS124S08 sinc3 filter and DRDY pin respond after the user initiates a conversion.

GUID-20220201-SS0I-KVRH-HGW8-KSB5SSZRJMNS-low.svgFigure 4-7 ADS124S08 Sinc3 Filter and DRDY Pin Behavior in Single-Shot Conversion Mode

In Figure 4-7, DRDY only transitions high-to-low to indicate new data are available after three conversion periods from conversion start (plus processing time). Importantly, the ADS124S08 automatically hides unsettled data after a conversion is triggered so that the user does not need to manually discard this information. However, this is not the case for all ADCs. For example, the DRDY pin on the 24-bit, 125-kSPS, 16-channel ADS1258 indicates all new conversion results in fixed-channel mode, even those values that are unsettled. Refer to the specific ADC data sheet for more information on how the device handles unsettled data.

Moreover, the ADS124S08 is only able to hide unsettled data because it receives the conversion start or register write request. These actions alert the ADC that the input signal is changing and that all information in the digital filter needs to be cleared. As stated in Section 4, the ADC cannot identify unsettled data if the analog input changes significantly while sampling the same channel, such as when a step input occurs. Another action that the ADC does not automatically recognize is when the inputs to an external multiplexer are changed. Similar to a step input, the user must manually restart the conversion process after changing the inputs on an external multiplexer.