The results from Figure 4-2 and Figure 4-3 yield an approximation for the conversion latency, t_CL, as per Equation 14:

where

• x is the sinc filter order, which is the x in the notation sinc^x

This relationship is implied in the ADS1261 conversion latency table introduced in Section 2. For example, the conversion latency for the 20 SPS ODR is 50.43 ms using a sinc¹ filter, which is approximately 1 / ODR. Comparatively, the latency is 150.4 ms using the sinc³ filter, which is approximately 3 / ODR. However, additional factors such as the ADC overhead time or programmable delay can skew this relationship. These factors are discussed in more detail throughout this document.

The digital filter behavior in response to a step input can also be seen in a real ADC. Figure 4-4 recreates an image from the ADS1261 data sheet that reveals how the data ready (DRDY) pin and sinc³ output (in blue) respond when a step input (in black) is applied to a single input channel.

The important takeaway from Figure 4-4 is that the two conversion results produced immediately after the step input (shown in red) are a mix of old data and new data. However, DRDY still transitions high-to-low to indicate new conversion results are ready even though these are comprised of unsettled data. In other words, the ADC does not detect when a step input is applied to the selected channel. Instead, the delta-sigma modulator continues to sample the input and the digital filter processes this information regardless of significant changes in the analog signal. As Figure 4-4 shows, the ADS1261 requires a number of additional DRDY transitions to produce settled conversion results (in green), which depends on the selected filter type. Ultimately, the user must manually identify a step input and then ignore subsequent DRDY transitions until a settled conversion result is available.

It is also important to consider if a step change occurs during the conversion process, which can lead to additional conversion latency. Figure 4-5 shows a step input occurring immediately before conversion period N+1 on a single channel (CH1). Figure 4-6 shows the same response with the input step occurring during conversion period N+1.

As Figure 4-6 shows, a sinc³ filter actually requires four conversion periods to produce a settled conversion result when the step input occurs during the conversion process. This additional delay occurs because the first digital filter stage contains sampled data from when the analog input was both –FS and +FS. This information is effectively useless for accurately recreating the input signal and needs to completely clear out of the digital filter before settled conversion results are available. This requires three complete conversion periods for a sinc³ filter, with settled data available at the end of the fourth conversion period.

Equation 3 applies this consideration to Equation 14 and provides an approximation for t_CL when the analog input changes significantly during the conversion process:

where

• x is the sinc filter order, which is the x in the notation sinc^x

To avoid reading unsettled conversion results as well as increasing conversion latency, ensure that the input signal has settled to its final value before starting the conversion process.