SBAA669 February   2025 ADC3548 , ADC3549 , ADC3568 , ADC3569 , ADC3648 , ADC3649 , ADC3664 , ADC3668 , ADC3669

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2AAF Tradeoffs at Low Frequency and Low Sampling Rate
  6. 3AAF Tradeoffs at Low Frequency and Higher Sampling Rate
  7. 4The Power of the ADC's Integrated DDC
  8. 5Summary
  9. 6References

Summary

In summary, increasing the sampling rate of the ADC and/or using an ADC with digital processing features play an important role in increasing the overall system DR performance. To be upfront, there can be a downside with a slight increase in the ADC’s power consumption when the DDC is employed. This is due to the higher sampling rate ADC and use of the extra digital features within the ADC. However, this can be a wash in terms of power if your application is still using an older generation ADC.

The analog tradeoffs involved in AAF design and the advantages of using DDC features to address dynamic range limitations have also been revealed. Keep in mind, these tradeoffs help to attack pesky HD2 and HD3 harmonics, but sometimes are not as effective on IMD3 spurious when using multi-tone signals, so further filtering can be required in certain applications.

Either way, the use of one or a combination of both techniques help to facilitate a healthier dynamic range for your next high-speed signal chain application, whether you're using the latest MSPS or GSPS ADCs available on the market.