SBAS891B November   2017  – September 2022 ADS7142-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: All Modes
    6. 6.6  Electrical Characteristics: Manual Mode
    7. 6.7  Electrical Characteristics: Autonomous Modes
    8. 6.8  Electrical Characteristics: High Precision Mode
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics: All Modes
    13. 6.13 Typical Characteristics: Manual Mode
    14. 6.14 Typical Characteristics: Autonomous Modes
    15. 6.15 Typical Characteristics: High-Precision Mode
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Input and Multiplexer
        1. 7.3.1.1 Two-Channel, Single-Ended Configuration
        2. 7.3.1.2 Single-Channel, Single-Ended Configuration With Remote Ground Sense
        3. 7.3.1.3 Single-Channel, Pseudo-Differential Configuration
      2. 7.3.2  Offset Calibration
      3. 7.3.3  Reference
      4. 7.3.4  ADC Transfer Function
      5. 7.3.5  Oscillator and Timing Control
      6. 7.3.6  I2C Address Selector
      7. 7.3.7  Data Buffer
        1. 7.3.7.1 Filling of the Data Buffer
        2. 7.3.7.2 Reading Data From the Data Buffer
      8. 7.3.8  Accumulator
      9. 7.3.9  Digital Window Comparator
      10. 7.3.10 I2C Protocol Features
        1. 7.3.10.1 General Call
        2. 7.3.10.2 General Call With Software Reset
        3. 7.3.10.3 General Call With Write Software Programmable Part of the Target Address
        4. 7.3.10.4 Configuring the ADC Into High-Speed I2C Mode
        5. 7.3.10.5 Bus Clear
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Power Up and Reset
      2. 7.4.2 Manual Mode
        1. 7.4.2.1 Manual Mode With CH0 Only
        2. 7.4.2.2 Manual Mode With AUTO Sequence
      3. 7.4.3 Autonomous Modes
        1. 7.4.3.1 Autonomous Mode With Threshold Monitoring and Diagnostics
          1. 7.4.3.1.1 Autonomous Mode With Pre-ALERT Data
          2. 7.4.3.1.2 Autonomous Mode With Post-ALERT Data
        2. 7.4.3.2 Autonomous Mode With Burst Data
          1. 7.4.3.2.1 Autonomous Mode With Start Burst
          2. 7.4.3.2.2 Autonomous Mode With Stop Burst
      4. 7.4.4 High-Precision Mode
    5. 7.5 Programming
      1. 7.5.1 Reading Registers
        1. 7.5.1.1 Single Register Read
        2. 7.5.1.2 Reading a Continuous Block of Registers
      2. 7.5.2 Writing Registers
        1. 7.5.2.1 Single Register Write
        2. 7.5.2.2 Writing a Continuous Block of Registers
        3. 7.5.2.3 Set Bit
        4. 7.5.2.4 Clear Bit
    6. 7.6 Register Map
      1. 7.6.1 Page1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 ADS7142-Q1 as a Programmable Comparator With False Trigger Prevention and Diagnostics
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Programmable Thresholds and Hysteresis
          2. 8.2.1.2.2 False Trigger Prevention With an Event Counter
          3. 8.2.1.2.3 Fault Diagnostics With the Data Buffer
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Voltage and Temperature Monitoring in Remote Camera Modules Using the ADS7142-Q1
        1. 8.2.2.1 Design Requirements
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD and DVDD Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Electrostatic Discharge Caution
    2. 9.2 Glossary
    3. 9.3 Trademarks
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Support Resources
  10. 10Mechanical, Packaging, and Orderable Information

6.6 Electrical Characteristics: Manual Mode

at TA = -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SAMPLING DYNAMICS
tconv Conversion time AVDD = 1.65 V to 3.6 V 1.8 µs
tacq Acquisition time AVDD = 1.65 V to 3.6 V 18 TSCL
tcycle Cycle time AVDD = 1.65 V to 3.6 V, SCL = 3.4 MHz 7.1 µs
DC SPECIFICATIONS
Resolution 12 Bits
NMC No missing codes AVDD = 1.65 V to 3.6 V 12 Bits
DNL Differential nonlinearity AVDD = 1.65 V to 3.6 V –0.99 ±0.3 1 LSB(1)
INL Integral nonlinearity –2.75 ±0.5 2.75 LSB
EO Offset error Post offset calibration –4 ±0.5 4 LSB
dVOS/dT Offset drift with temperature Post offset calibration 5 ppm/°C
EG Gain error –0.1 ±0.03 0.1 %FSR
Gain error drift with temperature 5 ppm/°C
AC SPECIFICATIONS
SNR(2) Signal-to-noise ratio fIN = 2 kHz, AVDD = 3 V,
fSAMPLE = 140 kSPS		 68.75 70 dB
fIN = 2 kHz, AVDD = 1.8 V,
fSAMPLE = 140 kSPS		 68
THD(2)(3) Total harmonic distortion fIN = 2 kHz, AVDD = 3 V,
fSAMPLE = 140 kSPS		 –85 dB
fIN = 2 kHz, AVDD = 1.8 V,
fSAMPLE = 140 kSPS		 –80
SINAD(2) Signal-to-noise and distortion fIN = 2 kHz, AVDD = 3 V,
fSAMPLE = 140 kSPS		 68.5 69.5 dB
fIN = 2 kHz, AVDD = 1.8 V,
fSAMPLE = 140 kSPS		 67.5
SFDR(2) Spurious-free dynamic range fIN = 2 kHz, AVDD = 3 V,
fSAMPLE = 140 kSPS		 90 dB
BW –3-dB small-signal bandwidth 25 MHz
POWER CONSUMPTION
IAVDD Analog supply current fSAMPLE = 140 kSPS, SCL = 3.4 MHz 265 300 µA
fSAMPLE= 5.5 kSPS, SCL = 100 kHz 8
fSAMPLE = 140 kSPS, SCL = 3.4 MHz, AVDD = 1.8 V 160
fSAMPLE = 5.5 kSPS, SCL = 100 kHz, AVDD = 1.8 V 5
IDVDD Digital supply current fSAMPLE = 140 kSPS, SCL = 3.4 MHz, SDA = AAA0h 25 µA
fSAMPLE = 5.5 kSPS, SCL = 100 kHz, SDA = AAA0h 2
fSAMPLE = 140 kSPS, SCL = 3.4 MHz, AVDD = 1.8 V, SDA = AAA0h 15
IAVDD Static analog supply current No activity on SCL and SDA 6 nA
IDVDD Static digital supply current No activity on SCL and SDA 2 nA
(1) LSB means least significant byte. See the ADC Transfer Function for details.
(2) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise specified.
(3) Calculated on the first nine harmonics of the input frequency.