SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.6.5 DDS Streaming Mode

DDS Stream mode allows to user to send a continuous stream of frequency/phase/amplitude values to the DDS using the JESD204C Interface. This mode is useful for frequency/phase/amplitude modulation/keying. Frequency streaming can also be used to generate complex chirp signals over a wide frequency range while using less JESD204C bandwidth compared to DUC mode.

To put a DSP channel into DDS Stream mode, program DSP_MODEn to DDS Stream mode. DDS Stream mode supports input sample rates of FDACCLK/16, FDACCLK/32, or FDACCLK/64. This is configured by programming the DSP_L register to set the DDS Upsampling factor to 16, 32, or 64. The user must select a JMODE that supports 16-bit samples and supports an LT value that matches the DDS Upsampling factor (16, 32, or 64).

Table 7-14 summarizes some key features of DDS Stream mode.

Table 7-14 Summary of DDS Streaming Mode
Property/Feature Details
Supported JMODEs: Any 16-bit JMODE that supports the desired setting for JESD_M and DSP_L
Number of JESD204C Converters (streams) allocated to each DDS channel:

2

(32-bits)
Supported Values for JESD_M: 2, 4, 6, 8
Supported Upsampling Factor (DSP_L): 16, 32, 64
Streaming Options

Stream frequency, phase, and amplitude (STREAM_MODE[n]=0)

Stream frequency only (STREAM_MODE[n]=1)

Stream phase and amplitude only (STREAM_MODE[n]=2)

Can trigger the DDS by streaming zero amplitude: Yes
Actions that occur when DDS is triggered: Update non-streamed parameters from FREQ/PHASE/AMP registers. Reset phase accumulator if NCO_AR is set.

Two 16-bit JESD204C converters (streams) are allocated to each DSP channel according to Table 7-15. The user must program JESD_M to make sure that each DSP channel (that is configured in DDS Stream mode) receives two 16-bit streams. The two 16-bit streams are concatenated to produce a single 32-bit stream (referred to as sdata). The lower stream is the lower 16-bits (sdata[15:0]). The upper stream is the upper 16-bits (sdata[31:16]).

Table 7-15 Allocation of JESD204C Converters to DSP Channels (DDS-Stream Mode)

JESD204C Converter (Stream)

DSP Channel Associated with the converter Contribution to the 32-bit DDS stream (sdata)
C0 DSP0 sdata[15:0]
C1 DSP0 sdata[31:16]
C2 DSP1 sdata[15:0]
C3 DSP1 sdata[31:16]
C4 DSP2 sdata[15:0]
C5 DSP2 sdata[31:16]
C6 DSP3 sdata[15:0]
C7 DSP3 sdata[31:16]

If FPA-Stream mode is enabled (STREAM_MODE[n]=0), the DDS interprets sdata[31:1] as frequency or phase+amplitude depending the value of sdata[0]. This is shown in Table 7-16 and Table 7-17. This allows the stream to control all parameters (frequency, phase, amplitude). The phase/amplitude samples are internally delayed by one input sample period (compared to frequency samples). This allows the user to simultaneously change all parameters by sending a phase+amplitude sample immediately followed by a frequency sample.

Table 7-16 Format of Frequency Sample (STREAM_MODE[n]=0)
sdata[31:1] sdata[0]

31-bit frequency value

(LSB weight is 2-31 * FDAC)

 1’b0
Table 7-17 Format of a Phase+Amplitude Sample (STREAM_MODE[n]=0)
sdata[31:16] sdata[15:1] sdata[0]

16-bit phase value

(LSB weight is 2-16 * 2π radians)

15-bit amplitude value (unsigned)

(LSB weight is 2-15 * full scale)

 1’b1

When frequency data is received, the previous phase and amplitude are held. When phase/amplitude data is received, the previous frequency is held. The initial frequency, phase, and amplitude are all zero when the DDS is first enabled (by SYS_EN).

The user can also trigger the DDS by streaming a zero-value amplitude and setting thephase LSB bit PHASE[0] = 1. If NCO_AR[n] is set, this resets the phase accumulator (it resumes accumulation once the signal amplitude is non-zero). This provides a convenient way to generate frequency chirps with a consistent initial phase.

In Frequency/Phase/Amplitude or Phase/Amplitude stream modes (STREAM_MODE[n] = 2), the frequency is determined by the FREQ registers.

In Frequency/Phase/Amplitude or Phase/Amplitude stream modes (STREAM_MODE[n] = 0 or 2), streaming a zero-value amplitude causes the DDS to start using any new value in the FREQ[n] register. This trigger is decoded internally by the DDS and operates independently from the trigger sources defined in DSP Triggering.

Since the JESD204C link can experience bit errors, this can corrupt the sdata[0] bit causing the frequency, phase, or amplitude to be corrupted. The user can periodically toggle sdata[0] to stream all parameters and make sure that any corruption is overwritten periodically. If the user prefers to always send frequency data or always send phase/amplitude data, use the STREAM_MODE register to instruct the DDS to ignore the sdata[0] bit entirely. The options are listed in Table 7-18.

Table 7-18 Stream Modes Description
STREAM_MODEn Description
0 FPA-Stream: Dynamically stream frequency/phase/amplitude using the sdata[0] bit.
1 F-Stream: Only stream frequency samples. The sdata[0] bit is the LSB of the frequency value, allowing 32-bit frequencies. Phase and amplitude are set by the PHASE[n] and AMP[n] registers.
2 PA-Stream: Only stream phase/amplitude samples (sdata[0] is ignored). Frequency is set by the FREQ[n] register.
Table 7-19 Format of Frequency Sample (STREAM_MODE[n]=1)
sdata[31:0]

32-bit frequency value

(LSB weight is 2-32 * FDAC)
Table 7-20 Format of a Phase+Amplitude Sample (STREAM_MODE[n]=2)
sdata[31:16] sdata[15:1] sdata[0]

16-bit phase value

(LSB weight is 2-16 * 2π radians)

15-bit amplitude value (unsigned)

(LSB weight is 2-15 * full scale)

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