SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.13 Datapath Registers

Table 8-233 lists the memory-mapped registers for the Datapath registers. All register offset addresses not listed in Table 8-233 should be considered as reserved locations and the register contents should not be modified.

Table 8-233 DATAPATH Registers
OffsetAcronymRegister NameSection
2E0hDSP_MODEGo
2E2hDSP_LGo
2E3hDSP_GAIN0Go
2E4hDSP_GAIN1Go
2E5hDSP_GAIN2Go
2E6hDSP_GAIN3Go
2E7hDSP_FORMATGo
2E8hDAC_SRCGo
2E9hDAC_SRC_ALTGo
2EAhMXMODEGo
2EBhTRUNC_HLSBGo
2EChDAC_DLY0Go
2EDhDAC_DLY1Go
2EEhDAC_INVGo

Complex bit access types are encoded to fit into small table cells. Table 8-234 shows the codes that are used for access types in this section.

Table 8-234 Datapath Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.3.13.1 DSP_MODE Register (Offset = 2E0h) [Reset = 0000h]

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Table 8-235 DSP_MODE Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h
14-12DSP_MODE3R/W0h DSP_MODE3 field defines the operational mode of DSP channel 3.

Note: Note: When all DSPs are disabled, the part automatically activates Bypass Mode (JESD samples are sent to the DACs).

There is no crossbar between the JESD interface and the DSP channels, it is important to assign DSP modes that require JESD samples to the lower DSP channel numbers (channel 0 thru JESD_M/2 – 1). Be sure to also program JESD_M appropriately. Use JESD_M=0 if no DSPs require JESD samples. See DSP mode.

Note: When DSP_L is configured for 4x or 6x interpolation, only DSP channel 0 and 1 can operate in DUC mode. The other channels must use a different mode (or be disabled).

Note: This register should only be changed when SYS_EN=0.

0h = DSP0 is disabled (unused)
1h = DUC mode – Sends JESD samples through the DUC
2h = DDS SPI mode – Uses DDS values from FREQ, PHASE, and AMP registers (JESD samples not used)
3h = DDS Vector mode – Uses DDS vector player to create DAC samples (JESD samples not used)
4h = DDS Stream mode– Uses DDS parameters streamed from JESD interface
5h = Reserved
6h = Reserved
7h = Reserved
11RESERVEDR0h
10-8DSP_MODE2R/W0h DSP_MODE2 field defines the operational mode of DSP channel 2 per table for DSP_MODE3
7RESERVEDR0h
6-4DSP_MODE1R/W0h DSP_MODE1 field defines the operational mode of DSP channel 1 per table for DSP_MODE3
3RESERVEDR0h
2-0DSP_MODE0R/W0h DSP_MODE0 field defines the operational mode of DSP channel 0 per table for DSP_MODE3

8.3.13.2 DSP_L Register (Offset = 2E2h) [Reset = 00h]

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Table 8-236 DSP_L Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h
3-0DSP_LR/W0h Specifies the DUC interpolation factor or the DDS Up-sampling Factor. DSP_L applies only when JESD_M is greater than 0 and at least one DSP channel is enabled (DSP_MODE). This typically means one or more DSP channels are configured for DUC mode or DDS Stream mode (see DSP_MODE). However, the JESD interface can also be used soley to provide a trigger for DSPs operating in DDS-SPI or DDS-Vector mode. All DSP channels share one setting.
all settings 0x3-0xF support DUC, DDS-SPI, DDS-Vector modes.
Note: If DSP channels are operating in various modes, you must select a DSP_L setting that supports all the active modes.
Note: This register should only be changed when SYS_EN=0.
0h = RESERVED
1h = RESERVED
2h = RESERVED
3h = [INT_4X] 4x
4h = [INT_6X] 6x
5h = [INT_8X] 8x
6h = [INT_12X] 12x
7h = [INT_16X] 16x (also for DDS Streaming Upsample Factor)
8h = [INT_24X] 24x
9h = [INT_32X] 32x (also for DDS Streaming Upsample Factor)
Ah = [INT_48X] 48x
Bh = [INT_64X] 64x (also for DDS Streaming Upsample Factor)
Ch = [INT_96X] 96x
Dh = [INT_128X] 128x
Eh = [INT_192X] 192x
Fh = [INT_256X] 256x

8.3.13.3 DSP_GAIN0 Register (Offset = 2E3h) [Reset = 00h]

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Table 8-237 DSP_GAIN0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h
6-4DSP_GAIN0_COARSER/W0h Adjusts the output coarse gain of DSP channel 0.
COARSE_GAIN = 2-VALUE
3-0DSP_GAIN0_FINER/W0h Adjusts the output fine gain of DSP channel 0.
FINE_GAIN = 1 - (VALUE/32)

8.3.13.4 DSP_GAIN1 Register (Offset = 2E4h) [Reset = 00h]

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Table 8-238 DSP_GAIN1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h
6-4DSP_GAIN1_COARSER/W0h Adjusts the output coarse gain of DSP channel 1.
COARSE_GAIN = 2-VALUE
3-0DSP_GAIN1_FINER/W0h Adjusts the output fine gain of DSP channel 1.
FINE_GAIN = 1 - (VALUE/32)

8.3.13.5 DSP_GAIN2 Register (Offset = 2E5h) [Reset = 00h]

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Table 8-239 DSP_GAIN2 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h
6-4DSP_GAIN2_COARSER/W0h Adjusts the output coarse gain of DSP channel 2.
COARSE_GAIN = 2-VALUE
3-0DSP_GAIN2_FINER/W0h Adjusts the output fine gain of DSP channel 2.
FINE_GAIN = 1 - (VALUE/32)

8.3.13.6 DSP_GAIN3 Register (Offset = 2E6h) [Reset = 00h]

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Table 8-240 DSP_GAIN3 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h
6-4DSP_GAIN3_COARSER/W0h Adjusts the output coarse gain of DSP channel 3.
COARSE_GAIN = 2-VALUE
3-0DSP_GAIN3_FINER/W0h Adjusts the output fine gain of DSP channel 3.
FINE_GAIN = 1 - (VALUE/32)

8.3.13.7 DSP_FORMAT Register (Offset = 2E7h) [Reset = 00h]

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Table 8-241 DSP_FORMAT Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0h
0DSP_FORMATR/W0h Choose real or imaginary output when the DSPs are configured for DUC mode or a DDS Mode (see DSP_MODE).
Note: This register affects DUC and DDS modes.
0h = [DSP_OUT_REAL] DSP outputs are real (DSP mixer converts complex to real by discarding the imaginary part). Up to 4 DSPs can be enabled.
1h = [DSP_OUT_COMP] DSP outputs are complex. Up to 2 DSPs can be enabled (DSP0 and DSP1). The mixer in DSP2 generates the imaginary samples for DSP0, so the user should bind a DAC to DSP2 using DAC_SRC. Similarly, if DSP1 is enabled, the mixer in DSP3 generates the imaginary samples for DSP1, so the user should bind a DAC to DSP3 to access those samples if desired. See Complex Output Support.

8.3.13.8 DAC_SRC Register (Offset = 2E8h) [Reset = 21h]

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Table 8-242 DAC_SRC Register Field Descriptions
BitFieldTypeResetDescription
7-4DAC_SRC1R/W2h In bypass mode (see DSP_MODE), DAC_SRC1 selects which input stream is sent to DACB. In DUC or DDS modes, DAC_SRC1 controls which DSP (DUC/DDS) outputs are routed (summed) to DACB. See Section DAC Source Selection
3-0DAC_SRC0R/W1h see DAC_SRC1

8.3.13.9 DAC_SRC_ALT Register (Offset = 2E9h) [Reset = 00h]

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Table 8-243 DAC_SRC_ALT Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0RESERVEDR0h Reserved

8.3.13.10 MXMODE Register (Offset = 2EAh) [Reset = 00h]

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Table 8-244 MXMODE Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h
6-4MXMODE1R/W0h Specify the DAC Output Mode for DACB.
0h = [NRZ] Normal mode (non-return-to-zero or NRZ) (sinc nulls at n*FS)
1h = [RF] RF Mode (return to inverse or RTI) (sinc nulls at DC and 2n*FS)
2h = [RTZ] Return-to-Zero (RTZ) (sinc nulls at 2n*FS)
3h = [DES2XL] DES2XL – Samples provided by the DES interpolator
4h = [DES2XH] DES2XH – Samples provided by the DES interpolator (high-pass mode)
5h = RESERVED
6h = [DISABLED] Disabled - DACB is disabled
7h = RESERVED
3RESERVEDR0h
2-0MXMODE0R/W0h See MXMODE0

8.3.13.11 TRUNC_HLSB Register (Offset = 2EBh) [Reset = 00h]

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Table 8-245 TRUNC_HLSB Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0h
0TRUNC_HLSBR/W0hWhen the output resolution of the DAC is less than 16-bits, the output is truncated to the proper resolution. If this bit is set, a 1/2 LSB offset is added to the truncated value to reduce the average offset introduced by truncation.

8.3.13.12 DAC_DLY0 Register (Offset = 2ECh) [Reset = 00h]

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Table 8-246 DAC_DLY0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h
5DAC_DLY0_ENR/W0h
0h = Disable adjustable delay for DACA (default)
1h = Enable adjustable delay for DACA
4-0DAC_DLY0_VALR/W0h Adjusts the delay for DACA. The added delay (in DACCLK cycles) is 64 + DAC_DLY0_VAL.
Note: Changing this register can produce glitches on the DAC output unless the sample stream is static during the change.

8.3.13.13 DAC_DLY1 Register (Offset = 2EDh) [Reset = 00h]

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Table 8-247 DAC_DLY1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h
5DAC_DLY1_ENR/W0h
0h = Disable adjustable delay for DACB (default)
1h = Enable adjustable delay for DACB
4-0DAC_DLY1_VALR/W0h Adjusts the delay for DACB. The added delay (in DACCLK cycles) is 64 + DAC_DLY1_VAL.
Note: Changing this register can produce glitches on the DAC output unless the sample stream is static during the change.

8.3.13.14 DAC_INV Register (Offset = 2EEh) [Reset = 00h]

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Table 8-248 DAC_INV Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR0h
1DAC_INV1R/W0h DAC1 output is inverted when set
0DAC_INV0R/W0h DAC0 output is inverted when set