SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.6 JESD204C Registers

Table 8-58 lists the memory-mapped registers for the JESD204C registers. All register offset addresses not listed in Table 8-58 should be considered as reserved locations and the register contents should not be modified.

Table 8-58 JESD204C Registers
OffsetAcronymRegister NameSection
0x101JMODESection 8.3.6.1
0x102JESD_MSection 8.3.6.2
0x103JCTRLSection 8.3.6.3
0x104SHMODESection 8.3.6.4
0x105KM1Section 8.3.6.5
0x106RBDSection 8.3.6.6
0x107JESD_STATUSSection 8.3.6.7
0x108REFDIVSection 8.3.6.8
0x10AMPYSection 8.3.6.9
0x10BRATESection 8.3.6.10

Complex bit access types are encoded to fit into small table cells. Table 8-59 shows the codes that are used for access types in this section.

Table 8-59 JESD204C Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
R-1R
-1		Read
Returns 1s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

8.3.6.1 JMODE Register (Offset = 0x101) [Reset = 0x00]

JMODE is shown in Table 8-60.

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Table 8-60 JMODE Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-0JMODER/W0x0 Specifies the JMODE

8.3.6.2 JESD_M Register (Offset = 0x102) [Reset = 0x01]

JESD_M is shown in Table 8-61.

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Table 8-61 JESD_M Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0JESD_MR/W0x1 Specify the number of sample streams (JESD204C converters) to enable (JESD204C M parameter). The number of enabled streams must be appropriate based on the number of DAC or DSP channels that are configured to receive samples from the JESD interface (see DSP_MODE, MXMODE, DAC_SRC, DSP_L). When JESD_M=0, the JESD interface will not be enabled when SYS_EN is set (e.g. if all DSP channels do not need input samples).
DSP_MODE = Bypass mode (all DSPs disabled), JESD_M must be 1 or 2. Use Use DAC_SRC to bind DAC channels to either input stream 0 or 1.
DSP_MODE = any DSPs enabled, JESD_M must be 0, 1, 2, 4, 6, 8. Enable 2 sample streams for each DSP channel that requires samples (see DSP_MODE). Use JESD_M=0 to disable the JESD interface if no DSPs require input samples.
Streams 0 and 1 supply DSP channel 0.
Streams 2 and 3 supply DSP channel 1.
Streams 4 and 5 supply DSP channel 2.
Streams 6 and 7 supply DSP channel 3.
Note 1: JESD_M should not exceed the Mx parameter associated with the selected JMODE. See Supported Modes for the Mx value associated with each JMODE.
The number of lanes enabled (L) is computed as L = ceiling(M/Mx*Lx).
Using JESD_M=1 is only legal in DSP mode if all enabled DSPs are using a non-JESD mode (e.g. DDS SPI or DDS Vector Mode). The single sample stream can be used for a trigger source (TRIG_TYPEn=3, TRIG_SELn=0). When triggering in this way, only JMODE 3 thru 7 are supported, and LT must be 32, 64, 128, or 256 (see DSP_L).

8.3.6.3 JCTRL Register (Offset = 0x103) [Reset = 0x03]

JCTRL is shown in Table 8-62.

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Table 8-62 JCTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0
6TI_MODER/W0x0
  • 0x0 = JESD204C standard mode (default)
  • 0x1 = Special TI mode (set this if using TI transmitter IP).
5SUBCLASSR/W0x0 Specify how the elastic buffer is released:
  • 0x0 = Subclass 0 operation (default). Release the elastic buffer immediately once all lanes have starting writing to the buffer.
  • 0x1 = Subclass 1 operation. Release the elastic buffer on a release opportunity defined by the LMFC/LEMC and RBD.
4JENCR/W0x0
  • 0x0 = Use 8b/10b link layer
  • 0x1 = Use 64b/66b link layer
3-2RESERVEDR0x0
1SFORMATR/W0x1 Input sample format for JESD204C samples.
If any DSP is configured in DSP-Stream mode, you must use SFORMAT=1.
  • 0x0 = Offset binary
  • 0x1 = Signed 2's complement (default)
0SCRR/W0x1 The 8b/10b scrambler is recommended to improve spurious noise and ensure that certain sample payloads cannot prevent the JESD204C receiver from detecting incorrect code-group or lane alignment. This register has no effect on 64b/66b modes (which are always scrambled).
  • 0x0 = 8b/10b Scrambler disabled
  • 0x1 = 8b/10b Scrambler enabled (default)

8.3.6.4 SHMODE Register (Offset = 0x104) [Reset = 0x00]

SHMODE is shown in Table 8-63.

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Table 8-63 SHMODE Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR0x0
1-0SHMODER/W0x0 Select the mode for the 64b/66b sync word (32 bits of data per multi-block). This only applies when JENC=1 (64b/66b mode).
Note: This device does not support any JESD204C command features. All command fields are ignored by the receiver.
  • 0x0 = Enable CRC-12 checking (JESD204C Table 41) (default setting)
  • 0x1 = RESERVED (for CRC-3, which is not supported)
  • 0x2 = Enable FEC (JESD204C Table 45)
  • 0x3 = RESERVED (for standalone command channel, which is not supported)

8.3.6.5 KM1 Register (Offset = 0x105) [Reset = 0x3F]

KM1 is shown in Table 8-64.

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Table 8-64 KM1 Register Field Descriptions
BitFieldTypeResetDescription
7-0KM1R/W0x3F K is the number of frames per multiframe, and K-1 shall be programmed here when using the 8b/10b link layer (see JENC). Depending on the JMODE setting, there are constraints on the legal values of K. Programming an illegal value for K will cause the link to malfunction.
The default value is KM1=31, which corresponds to K=32.
Note: For modes using the 64b/66b link layer, the KM1 register is ignored. The effective value of K is 256*E/F.

8.3.6.6 RBD Register (Offset = 0x106) [Reset = 0x80]

RBD is shown in Table 8-65.

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Table 8-65 RBD Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0
6-0RBDR/W0x0 This register shifts the elastic buffer release opportunities. Increasing RBD by 1 delays the release opportunities by 8 bytes (octets).
For 8b/10b modes, the legal RBD range is 0 to K*F/8-1.
For 64b/66b modes, the legal RBD range is 0 to 32*E-1.

8.3.6.7 JESD_STATUS Register (Offset = 0x107) [Reset = 0xXX]

JESD_STATUS is shown in Table 8-66.

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Table 8-66 JESD_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7EB_ERRW1CX Elastic buffer experienced underflow/overflow.
5JSYNC_STATERX Returns the state of the JESD204C SYNC signal.
0 = 0b0 = SYNC asserted
1 = 0b1 = SYNC de-asserted
4RESERVEDRX
3JESD_ALIGNEDRX Indicates that the LMFC/LEMC has been aligned by SYSREF and another SYSREF pulse has confirmed the alignment. This bit is read-only (cannot be cleared via SPI). After SYSREF_ALIGN_EN and SYS_EN are set, the part may require up to 15 SYSREF pulses to achieve alignment and set this bit.
2PLL_LOCKEDRX When high, indicates that all enabled PHY PLLs are locked.
1-0RESERVEDRX

8.3.6.8 REFDIV Register (Offset = 0x108) [Reset = 0x0030]

REFDIV is shown in Table 8-67.

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Table 8-67 REFDIV Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0x0
7-0REFDIVR/W0x30 Specifies the frequency divisor to generate the PHY PLL reference clock (FREF) from the DAC clock (FDACCLK).
The following values are legal: 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40, 48, 64, 80, 96 and 128.
All other values are reserved and produce undefined behavior.
See PLL Control.

8.3.6.9 MPY Register (Offset = 0x10A) [Reset = 0x0A]

MPY is shown in Table 8-68.

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Table 8-68 MPY Register Field Descriptions
BitFieldTypeResetDescription
7-0MPYR/W0xA Specifies the PLL frequency multiplier for the PHY. See PLL Control. The following values are legal for this design:
8 (0x8) = 8x
10 (0xA) = 10x
16 (0x10) = 16x
20 (0x14) = 20x
33 (0x21) = 33x
40 (0x28) = 40x
66 (0x42) = 66x
99 (0x63) = 99x

8.3.6.10 RATE Register (Offset = 0x10B) [Reset = 0x00]

RATE is shown in Table 8-69.

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Table 8-69 RATE Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR0x0
2-0RATER/W0x0 Controls the frequency multiplier from the Serdes VCO frequency FVCO to the Serdes bit rate FBIT. Affects all lanes. See Serdes PLL section.
  • 0x0 = 2x
  • 0x1 = 1x
  • 0x2 = 0.5x
  • 0x3 = 0.25x
  • 0x4 = 0.125x
  • 0x5 = Reserved
  • 0x6 = Reserved
  • 0x7 = Reserved