SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.7 JESD204C_Advanced Registers

Table 8-70 lists the memory-mapped registers for the JESD204C_Advanced registers. All register offset addresses not listed in Table 8-70 should be considered as reserved locations and the register contents should not be modified.

Table 8-70 JESD204C_ADVANCED Registers
OffsetAcronymRegister NameSection
0x120JSYNC_NSection 8.3.7.1
0x121JTESTSection 8.3.7.2
0x122JEXTRASection 8.3.7.3
0x124JTIMERSection 8.3.7.4
0x125JESD_RSTSection 8.3.7.5
0x127SYNC_EPWSection 8.3.7.6
0x128DI_THSection 8.3.7.7
0x12CLANE_ARSTATSection 8.3.7.8
0x12ELANE_INVSection 8.3.7.9
0x130LANE_SEL_0Section 8.3.7.10
0x131LANE_SEL_1Section 8.3.7.11
0x132LANE_SEL_2Section 8.3.7.12
0x133LANE_SEL_3Section 8.3.7.13
0x134LANE_SEL_4Section 8.3.7.14
0x135LANE_SEL_5Section 8.3.7.15
0x136LANE_SEL_6Section 8.3.7.16
0x137LANE_SEL_7Section 8.3.7.17
0x138LANE_SEL_8Section 8.3.7.18
0x139LANE_SEL_9Section 8.3.7.19
0x13ALANE_SEL_10Section 8.3.7.20
0x13BLANE_SEL_11Section 8.3.7.21
0x13CLANE_SEL_12Section 8.3.7.22
0x13DLANE_SEL_13Section 8.3.7.23
0x13ELANE_SEL_14Section 8.3.7.24
0x13FLANE_SEL_15Section 8.3.7.25
0x140LANE_ARR_0Section 8.3.7.26
0x141LANE_ARR_1Section 8.3.7.27
0x142LANE_ARR_2Section 8.3.7.28
0x143LANE_ARR_3Section 8.3.7.29
0x144LANE_ARR_4Section 8.3.7.30
0x145LANE_ARR_5Section 8.3.7.31
0x146LANE_ARR_6Section 8.3.7.32
0x147LANE_ARR_7Section 8.3.7.33
0x148LANE_ARR_8Section 8.3.7.34
0x149LANE_ARR_9Section 8.3.7.35
0x14ALANE_ARR_10Section 8.3.7.36
0x14BLANE_ARR_11Section 8.3.7.37
0x14CLANE_ARR_12Section 8.3.7.38
0x14DLANE_ARR_13Section 8.3.7.39
0x14ELANE_ARR_14Section 8.3.7.40
0x14FLANE_ARR_15Section 8.3.7.41
0x150LANE_STATUS_0Section 8.3.7.42
0x151LANE_STATUS_1Section 8.3.7.43
0x152LANE_STATUS_2Section 8.3.7.44
0x153LANE_STATUS_3Section 8.3.7.45
0x154LANE_STATUS_4Section 8.3.7.46
0x155LANE_STATUS_5Section 8.3.7.47
0x156LANE_STATUS_6Section 8.3.7.48
0x157LANE_STATUS_7Section 8.3.7.49
0x158LANE_STATUS_8Section 8.3.7.50
0x159LANE_STATUS_9Section 8.3.7.51
0x15ALANE_STATUS_10Section 8.3.7.52
0x15BLANE_STATUS_11Section 8.3.7.53
0x15CLANE_STATUS_12Section 8.3.7.54
0x15DLANE_STATUS_13Section 8.3.7.55
0x15ELANE_STATUS_14Section 8.3.7.56
0x15FLANE_STATUS_15Section 8.3.7.57
0x160LANE_ERROR_0Section 8.3.7.58
0x161LANE_ERROR_1Section 8.3.7.59
0x162LANE_ERROR_2Section 8.3.7.60
0x163LANE_ERROR_3Section 8.3.7.61
0x164LANE_ERROR_4Section 8.3.7.62
0x165LANE_ERROR_5Section 8.3.7.63
0x166LANE_ERROR_6Section 8.3.7.64
0x167LANE_ERROR_7Section 8.3.7.65
0x168LANE_ERROR_8Section 8.3.7.66
0x169LANE_ERROR_9Section 8.3.7.67
0x16ALANE_ERROR_10Section 8.3.7.68
0x16BLANE_ERROR_11Section 8.3.7.69
0x16CLANE_ERROR_12Section 8.3.7.70
0x16DLANE_ERROR_13Section 8.3.7.71
0x16ELANE_ERROR_14Section 8.3.7.72
0x16FLANE_ERROR_15Section 8.3.7.73
0x170FIFO_STATUS_0Section 8.3.7.74
0x171FIFO_STATUS_1Section 8.3.7.75
0x172FIFO_STATUS_2Section 8.3.7.76
0x173FIFO_STATUS_3Section 8.3.7.77
0x174FIFO_STATUS_4Section 8.3.7.78
0x175FIFO_STATUS_5Section 8.3.7.79
0x176FIFO_STATUS_6Section 8.3.7.80
0x177FIFO_STATUS_7Section 8.3.7.81
0x178FIFO_STATUS_8Section 8.3.7.82
0x179FIFO_STATUS_9Section 8.3.7.83
0x17AFIFO_STATUS_10Section 8.3.7.84
0x17BFIFO_STATUS_11Section 8.3.7.85
0x17CFIFO_STATUS_12Section 8.3.7.86
0x17DFIFO_STATUS_13Section 8.3.7.87
0x17EFIFO_STATUS_14Section 8.3.7.88
0x17FFIFO_STATUS_15Section 8.3.7.89
0x18AJCAP_ARMSection 8.3.7.90
0x18BJCAP_MODESection 8.3.7.91
0x18CJCAP_OFFSETSection 8.3.7.92
0x18EJCAP_PAGESection 8.3.7.93
0x18FJCAP_STATUSSection 8.3.7.94
0x190JCAPSection 8.3.7.95
0x1A0LEC_CTRLSection 8.3.7.96
0x1B0LEC_CNT_0Section 8.3.7.97
0x1B1LEC_CNT_1Section 8.3.7.98
0x1B2LEC_CNT_2Section 8.3.7.99
0x1B3LEC_CNT_3Section 8.3.7.100
0x1B4LEC_CNT_4Section 8.3.7.101
0x1B5LEC_CNT_5Section 8.3.7.102
0x1B6LEC_CNT_6Section 8.3.7.103
0x1B7LEC_CNT_7Section 8.3.7.104
0x1B8LEC_CNT_8Section 8.3.7.105
0x1B9LEC_CNT_9Section 8.3.7.106
0x1BALEC_CNT_10Section 8.3.7.107
0x1BBLEC_CNT_11Section 8.3.7.108
0x1BCLEC_CNT_12Section 8.3.7.109
0x1BDLEC_CNT_13Section 8.3.7.110
0x1BELEC_CNT_14Section 8.3.7.111
0x1BFLEC_CNT_15Section 8.3.7.112

Complex bit access types are encoded to fit into small table cells. Table 8-71 shows the codes that are used for access types in this section.

Table 8-71 JESD204C_Advanced Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

8.3.7.1 JSYNC_N Register (Offset = 0x120) [Reset = 0x01]

JSYNC_N is shown in Table 8-72.

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Table 8-72 JSYNC_N Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0JSYNC_NR/W0x1 Set this bit to 0 to manually assert the SYNC~ signal. For normal operation, leave this bit set to 1.

8.3.7.2 JTEST Register (Offset = 0x121) [Reset = 0x00]

JTEST is shown in Table 8-73.

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Table 8-73 JTEST Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0x0
4-0JTESTR/W0x0 Sets PRBS mode. 0x5 and higher are RESERVED. See BER_EN.
  • 0x0 = Test mode disabled (normal operation)
  • 0x1 = PRBS7
  • 0x2 = PRBS9
  • 0x3 = PRBS15
  • 0x4 = PRBS31

8.3.7.3 JEXTRA Register (Offset = 0x122) [Reset = 0x0000]

JEXTRA is shown in Table 8-74.

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Table 8-74 JEXTRA Register Field Descriptions
BitFieldTypeResetDescription
15-1EXTRA_LANER/W0x0 Program JEXTRA to enable extra logical lanes (even if the selected JMODE does not utilized the lanes). EXTRA_LANE[n] enables lane n (n=1 to 15). This register enables the link layers. To also enable the PHY for the extra lanes, set EXTRA_PHY=1.
Note: The bit-rate and mode of the extra lanes are set by JMODE and JTEST registers.
0EXTRA_PHYR/W0x0
  • 0x0 = Only the link layers for extra lanes are enabled. Use this mode to evaluate the switching noise from the extra lanes. The PHY associated with each extra lane is not forced on. To provide input data to the extra lanes, it may be useful to use LANE_SELn to bind the extra logical lanes to PHY lanes that are bound to primary active lanes (logical lanes 0 to L-1)
  • 0x1 = The PHY layer for the extra lanes are also enabled. Use this mode to receive data from extra physical lanes. This should be done if you want to run BER testing on more lanes than JMODE enables, or run other PHY tasks on those lanes (eye scan, etc.)

8.3.7.4 JTIMER Register (Offset = 0x124) [Reset = 0x00]

JTIMER is shown in Table 8-75.

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Table 8-75 JTIMER Register Field Descriptions
BitFieldTypeResetDescription
7JTPLLR/W0x0 If this bit is set, the PHY PLL, bias, reference divider, and receiver analog is also reset when the watchdog timer expires.If this bit is 0, only the PHY receiver digital logic is reset.
6RESERVEDR0x0
5-4JTRR/W0x0 This register determines how much the watchdog counter is decremented when the link is up and DI_FAULT is not set.
See Watchdog Timer (JTIMER) for full details.
  • 0x0 = 1
  • 0x1 = 2
  • 0x2 = 8
  • 0x3 = 16
3RESERVEDR0x0
2-0JTTR/W0x0 JESD204C watchdog counter threshold. When the watchdog counter reaches the threshold defined by JTT, the PHY layer is reset (including the PHY PLL(s) if JTPLL=1) and the watchdog timer is reset. Larger values of JTT cause the watchdog timer to take longer to intervene.
See Watchdog Timer (JTIMER) for full details.
Note: The watchdog may not detect link up events shorter than 211 (2048) DACCLK cycles.
  • 0x0 = Watchdog timer disabled
  • 0x1 = 217
  • 0x2 = 219
  • 0x3 = 221
  • 0x4 = 223
  • 0x5 = Reserved
  • 0x6 = Reserved
  • 0x7 = Reserved

8.3.7.5 JESD_RST Register (Offset = 0x125) [Reset = 0x00]

JESD_RST is shown in Table 8-76.

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Table 8-76 JESD_RST Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0JESD_RSTR/W0x0 When set, this bit holds the digital portion of the JESD circuitry in reset but does not affect the PHY.

8.3.7.6 SYNC_EPW Register (Offset = 0x127) [Reset = 0x00]

SYNC_EPW is shown in Table 8-77.

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Table 8-77 SYNC_EPW Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR0x0
2-0SYNC_EPWR/W0x0 Specifies the pulse width of SYNC that is used for reporting errors to the transmitter. When an error is detected that does not require link resynchronization, SYNC is asserted for SYNC_EPW link clock cycles (equal to 8 *SYNC_EPW character durations). To disable error reporting over SYNC~, set SYNC_EPW=0. The legal range for SYNC_EPW is 0 to 4.
The reported errors are listed in Link Error Reports.

8.3.7.7 DI_TH Register (Offset = 0x128) [Reset = 0x00]

DI_TH is shown in Table 8-78.

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Table 8-78 DI_TH Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-2DI_ERR_REC R/W0x0 Specify how many contiguous, error-free multiblocks must be received to reset the Data Integrity error counter (and un-trigger the Data Integrity alarm if triggered).
  • 0x0 = 1 multiblock
  • 0x1 = 4 multiblocks
  • 0x2 = 16 multiblocks
  • 0x3 = 64 multiblocks
1-0DI_ERR_THR/W0x0 Specify how many multi-blocks must have Data Integrity errors to trigger the Data Integrity alarm. The receiver counts each error, but if a run of error-free multi-blocks occurs (as specified by DI_ERR_REC), the error counter resets.
  • 0x0 = 1 multiblock
  • 0x1 = 2 multiblocks
  • 0x2 = 4 multiblocks
  • 0x3 = 8 multiblocks

8.3.7.8 LANE_ARSTAT Register (Offset = 0x12C) [Reset = 0xXX]

LANE_ARSTAT is shown in Table 8-79.

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Table 8-79 LANE_ARSTAT Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDRX
0LANE_ARR_RDYW1CX This bit is set when lane arrival times are captured and available for read in LANE_ARR. Lane arrival data is captured when all lanes are ready and the chip attempts to release the elastic buffer. This bit is cleared when SYS_EN=0 or JESD_RST=1. Write 1 to clear this bit and allow the lane arrival data to be recaptured.

8.3.7.9 LANE_INV Register (Offset = 0x12E) [Reset = 0x0000]

LANE_INV is shown in Table 8-80.

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Table 8-80 LANE_INV Register Field Descriptions
BitFieldTypeResetDescription
15-0LANE_INVR/W0x0 Program LANE_INV[n]=1 to invert the bitstream through physical lane n. Use this if the differential pair is swapped between the transmitter and receiver.

8.3.7.10 LANE_SEL_0 Register (Offset = 0x130) [Reset = 0x00]

LANE_SEL_0 is shown in Table 8-81.

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Table 8-81 LANE_SEL_0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[0]R/W0x0 Specify which physical lane (0 to 15) is bound to logical lane 0. To bind physical lane p to logical lane n, program LANE_SEL[n]=p. For example, to bind logical lane 0 to physical lane 3, program LANE_SEL[0]=3.

8.3.7.11 LANE_SEL_1 Register (Offset = 0x131) [Reset = 0x01]

LANE_SEL_1 is shown in Table 8-82.

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Table 8-82 LANE_SEL_1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[1]R/W0x1 Specify which physical lane (0 to 15) is bound to logical lane 1.

8.3.7.12 LANE_SEL_2 Register (Offset = 0x132) [Reset = 0x02]

LANE_SEL_2 is shown in Table 8-83.

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Table 8-83 LANE_SEL_2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[2]R/W0x2 Specify which physical lane (0 to 15) is bound to logical lane 2.

8.3.7.13 LANE_SEL_3 Register (Offset = 0x133) [Reset = 0x03]

LANE_SEL_3 is shown in Table 8-84.

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Table 8-84 LANE_SEL_3 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[3]R/W0x3 Specify which physical lane (0 to 15) is bound to logical lane 3.

8.3.7.14 LANE_SEL_4 Register (Offset = 0x134) [Reset = 0x04]

LANE_SEL_4 is shown in Table 8-85.

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Table 8-85 LANE_SEL_4 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[4]R/W0x4 Specify which physical lane (0 to 15) is bound to logical lane 4.

8.3.7.15 LANE_SEL_5 Register (Offset = 0x135) [Reset = 0x05]

LANE_SEL_5 is shown in Table 8-86.

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Table 8-86 LANE_SEL_5 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[5]R/W0x5 Specify which physical lane (0 to 15) is bound to logical lane 5.

8.3.7.16 LANE_SEL_6 Register (Offset = 0x136) [Reset = 0x06]

LANE_SEL_6 is shown in Table 8-87.

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Table 8-87 LANE_SEL_6 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[6]R/W0x6 Specify which physical lane (0 to 15) is bound to logical lane 6.

8.3.7.17 LANE_SEL_7 Register (Offset = 0x137) [Reset = 0x07]

LANE_SEL_7 is shown in Table 8-88.

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Table 8-88 LANE_SEL_7 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[7]R/W0x7 Specify which physical lane (0 to 15) is bound to logical lane 7.

8.3.7.18 LANE_SEL_8 Register (Offset = 0x138) [Reset = 0x08]

LANE_SEL_8 is shown in Table 8-89.

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Table 8-89 LANE_SEL_8 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[8]R/W0x8 Specify which physical lane (0 to 15) is bound to logical lane 8.

8.3.7.19 LANE_SEL_9 Register (Offset = 0x139) [Reset = 0x09]

LANE_SEL_9 is shown in Table 8-90.

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Table 8-90 LANE_SEL_9 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[9]R/W0x9 Specify which physical lane (0 to 15) is bound to logical lane 9.

8.3.7.20 LANE_SEL_10 Register (Offset = 0x13A) [Reset = 0x0A]

LANE_SEL_10 is shown in Table 8-91.

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Table 8-91 LANE_SEL_10 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[10]R/W0xA Specify which physical lane (0 to 15) is bound to logical lane 10.

8.3.7.21 LANE_SEL_11 Register (Offset = 0x13B) [Reset = 0x0B]

LANE_SEL_11 is shown in Table 8-92.

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Table 8-92 LANE_SEL_11 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[11]R/W0xB Specify which physical lane (0 to 15) is bound to logical lane 11.

8.3.7.22 LANE_SEL_12 Register (Offset = 0x13C) [Reset = 0x0C]

LANE_SEL_12 is shown in Table 8-93.

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Table 8-93 LANE_SEL_12 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[12]R/W0xC Specify which physical lane (0 to 15) is bound to logical lane 12.

8.3.7.23 LANE_SEL_13 Register (Offset = 0x13D) [Reset = 0x0D]

LANE_SEL_13 is shown in Table 8-94.

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Table 8-94 LANE_SEL_13 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[13]R/W0xD Specify which physical lane (0 to 15) is bound to logical lane 13.

8.3.7.24 LANE_SEL_14 Register (Offset = 0x13E) [Reset = 0x0E]

LANE_SEL_14 is shown in Table 8-95.

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Table 8-95 LANE_SEL_14 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[14]R/W0xE Specify which physical lane (0 to 15) is bound to logical lane 14.

8.3.7.25 LANE_SEL_15 Register (Offset = 0x13F) [Reset = 0x0F]

LANE_SEL_15 is shown in Table 8-96.

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Table 8-96 LANE_SEL_15 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0LANE_SEL[15]R/W0xF Specify which physical lane (0 to 15) is bound to logical lane 15.

8.3.7.26 LANE_ARR_0 Register (Offset = 0x140) [Reset = 0xXX]

LANE_ARR_0 is shown in Table 8-97.

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Table 8-97 LANE_ARR_0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0
6-0LANE_ARR[0]RX Returns the arrival time of lane 0 (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF. For 8b/10b, the value returned can be between 0 and 31 (inclusive), regardless of the multiframe length. For 64b/66b, the value returned can be between 0 and 32*E-1 (inclusive). These registers are valid only when LANE_ARR_RDY=1.

8.3.7.27 LANE_ARR_1 Register (Offset = 0x141) [Reset = 0xXX]

LANE_ARR_1 is shown in Table 8-98.

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Table 8-98 LANE_ARR_1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX Reserved
6-0LANE_ARR[1]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.28 LANE_ARR_2 Register (Offset = 0x142) [Reset = 0xXX]

LANE_ARR_2 is shown in Table 8-99.

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Table 8-99 LANE_ARR_2 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[2]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.29 LANE_ARR_3 Register (Offset = 0x143) [Reset = 0xXX]

LANE_ARR_3 is shown in Table 8-100.

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Table 8-100 LANE_ARR_3 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[3]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.30 LANE_ARR_4 Register (Offset = 0x144) [Reset = 0xXX]

LANE_ARR_4 is shown in Table 8-101.

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Table 8-101 LANE_ARR_4 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[4]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.31 LANE_ARR_5 Register (Offset = 0x145) [Reset = 0xXX]

LANE_ARR_5 is shown in Table 8-102.

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Table 8-102 LANE_ARR_5 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[5]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.32 LANE_ARR_6 Register (Offset = 0x146) [Reset = 0xXX]

LANE_ARR_6 is shown in Table 8-103.

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Table 8-103 LANE_ARR_6 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[6]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.33 LANE_ARR_7 Register (Offset = 0x147) [Reset = 0xXX]

LANE_ARR_7 is shown in Table 8-104.

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Table 8-104 LANE_ARR_7 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[7]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.34 LANE_ARR_8 Register (Offset = 0x148) [Reset = 0xXX]

LANE_ARR_8 is shown in Table 8-105.

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Table 8-105 LANE_ARR_8 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[8]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.35 LANE_ARR_9 Register (Offset = 0x149) [Reset = 0xXX]

LANE_ARR_9 is shown in Table 8-106.

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Table 8-106 LANE_ARR_9 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[9]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.36 LANE_ARR_10 Register (Offset = 0x14A) [Reset = 0xXX]

LANE_ARR_10 is shown in Table 8-107.

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Table 8-107 LANE_ARR_10 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[10]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.37 LANE_ARR_11 Register (Offset = 0x14B) [Reset = 0xXX]

LANE_ARR_11 is shown in Table 8-108.

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Table 8-108 LANE_ARR_11 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[11]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.38 LANE_ARR_12 Register (Offset = 0x14C) [Reset = 0xXX]

LANE_ARR_12 is shown in Table 8-109.

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Table 8-109 LANE_ARR_12 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[12]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.39 LANE_ARR_13 Register (Offset = 0x14D) [Reset = 0xXX]

LANE_ARR_13 is shown in Table 8-110.

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Table 8-110 LANE_ARR_13 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[13]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.40 LANE_ARR_14 Register (Offset = 0x14E) [Reset = 0xXX]

LANE_ARR_14 is shown in Table 8-111.

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Table 8-111 LANE_ARR_14 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[14]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.41 LANE_ARR_15 Register (Offset = 0x14F) [Reset = 0xXX]

LANE_ARR_15 is shown in Table 8-112.

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Table 8-112 LANE_ARR_15 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX
6-0LANE_ARR[15]RX Returns the arrival time (in units of octa-bytes) with respect to the internal LMFC/LEMC that is established by SYSREF.

8.3.7.42 LANE_STATUS_0 Register (Offset = 0x150) [Reset = 0xXX]

LANE_STATUS_0 is shown in Table 8-113.

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Table 8-113 LANE_STATUS_0 Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDRX
2F_EMB_SYNCRX Returns 1 if logical lane 0 has frame or EMB synchronization.
1CG_BK_SYNCRX Returns 1 if logical lane 0 has code-group or block synchronization.
0SIG_DETRX Returns 1 if logical lane 0 is detecting a data signal

8.3.7.43 LANE_STATUS_1 Register (Offset = 0x151) [Reset = 0xXX]

LANE_STATUS_1 is shown in Table 8-114.

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Table 8-114 LANE_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[1]RX See registers and description for LANE_STATUS[0]

8.3.7.44 LANE_STATUS_2 Register (Offset = 0x152) [Reset = 0xXX]

LANE_STATUS_2 is shown in Table 8-115.

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Table 8-115 LANE_STATUS_2 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[2]RX See registers and description for LANE_STATUS[0]

8.3.7.45 LANE_STATUS_3 Register (Offset = 0x153) [Reset = 0xXX]

LANE_STATUS_3 is shown in Table 8-116.

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Table 8-116 LANE_STATUS_3 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[3]RX See registers and description for LANE_STATUS[0]

8.3.7.46 LANE_STATUS_4 Register (Offset = 0x154) [Reset = 0xXX]

LANE_STATUS_4 is shown in Table 8-117.

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Table 8-117 LANE_STATUS_4 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[4]RX See registers and description for LANE_STATUS[0]

8.3.7.47 LANE_STATUS_5 Register (Offset = 0x155) [Reset = 0xXX]

LANE_STATUS_5 is shown in Table 8-118.

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Table 8-118 LANE_STATUS_5 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[5]RX See registers and description for LANE_STATUS[0]

8.3.7.48 LANE_STATUS_6 Register (Offset = 0x156) [Reset = 0xXX]

LANE_STATUS_6 is shown in Table 8-119.

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Table 8-119 LANE_STATUS_6 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[6]RX See registers and description for LANE_STATUS[0]

8.3.7.49 LANE_STATUS_7 Register (Offset = 0x157) [Reset = 0xXX]

LANE_STATUS_7 is shown in Table 8-120.

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Table 8-120 LANE_STATUS_7 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[7]RX See registers and description for LANE_STATUS[0]

8.3.7.50 LANE_STATUS_8 Register (Offset = 0x158) [Reset = 0xXX]

LANE_STATUS_8 is shown in Table 8-121.

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Table 8-121 LANE_STATUS_8 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[8]RX See registers and description for LANE_STATUS[0]

8.3.7.51 LANE_STATUS_9 Register (Offset = 0x159) [Reset = 0xXX]

LANE_STATUS_9 is shown in Table 8-122.

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Table 8-122 LANE_STATUS_9 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[9]RX See registers and description for LANE_STATUS[0]

8.3.7.52 LANE_STATUS_10 Register (Offset = 0x15A) [Reset = 0xXX]

LANE_STATUS_10 is shown in Table 8-123.

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Table 8-123 LANE_STATUS_10 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[10]RX See registers and description for LANE_STATUS[0]

8.3.7.53 LANE_STATUS_11 Register (Offset = 0x15B) [Reset = 0xXX]

LANE_STATUS_11 is shown in Table 8-124.

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Table 8-124 LANE_STATUS_11 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[11]RX See registers and description for LANE_STATUS[0]

8.3.7.54 LANE_STATUS_12 Register (Offset = 0x15C) [Reset = 0xXX]

LANE_STATUS_12 is shown in Table 8-125.

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Table 8-125 LANE_STATUS_12 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[12]RX See registers and description for LANE_STATUS[0]

8.3.7.55 LANE_STATUS_13 Register (Offset = 0x15D) [Reset = 0xXX]

LANE_STATUS_13 is shown in Table 8-126.

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Table 8-126 LANE_STATUS_13 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[13]RX See registers and description for LANE_STATUS[0]

8.3.7.56 LANE_STATUS_14 Register (Offset = 0x15E) [Reset = 0xXX]

LANE_STATUS_14 is shown in Table 8-127.

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Table 8-127 LANE_STATUS_14 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[14]RX See registers and description for LANE_STATUS[0]

8.3.7.57 LANE_STATUS_15 Register (Offset = 0x15F) [Reset = 0xXX]

LANE_STATUS_15 is shown in Table 8-128.

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Table 8-128 LANE_STATUS_15 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_STATUS[15]RX See registers and description for LANE_STATUS[0]

8.3.7.58 LANE_ERROR_0 Register (Offset = 0x160) [Reset = 0xXX]

LANE_ERROR_0 is shown in Table 8-129.

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Table 8-129 LANE_ERROR_0 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[0]W1CX Sticky bits indicating various errors on lane 0.
  • 0x0 = Gearbox FIFO overflowed or underflowed. As long as the write clock frequency is correct the gearbox write clock can drift at least 3UI after this flag without causing data corruption.
  • 0x1 = Disparity error (8b/10b) or invalid sync header (64b/66b) occurred.
  • 0x2 = Not-in-table or unexpected control character (8b/10b) or Data Integrity (64b/66b) error occurred.
  • 0x3 = Reserved
  • 0x4 = Code-group or block synchronization was lost.
  • 0x5 = Frame alignment was lost (8b/10b only) or DI_FAULTis 1 (64b/66b).
  • 0x6 = Multi-frame, multi-block, or extended-multi-block alignment lost.
  • 0x7 = Alignment character found at unexpected location (8b/10b) or (extended)-multi-block pilot signal not in expected location (64b/66b)

8.3.7.59 LANE_ERROR_1 Register (Offset = 0x161) [Reset = 0xXX]

LANE_ERROR_1 is shown in Table 8-130.

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Table 8-130 LANE_ERROR_1 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[1]W1CX Sticky bits indicating various errors on lane 1. See description for LANE_ERROR[0]

8.3.7.60 LANE_ERROR_2 Register (Offset = 0x162) [Reset = 0xXX]

LANE_ERROR_2 is shown in Table 8-131.

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Table 8-131 LANE_ERROR_2 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[2]W1CX Sticky bits indicating various errors on lane 2. See description for LANE_ERROR[0]

8.3.7.61 LANE_ERROR_3 Register (Offset = 0x163) [Reset = 0xXX]

LANE_ERROR_3 is shown in Table 8-132.

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Table 8-132 LANE_ERROR_3 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[3]W1CX Sticky bits indicating various errors on lane 3. See description for LANE_ERROR[0]

8.3.7.62 LANE_ERROR_4 Register (Offset = 0x164) [Reset = 0xXX]

LANE_ERROR_4 is shown in Table 8-133.

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Table 8-133 LANE_ERROR_4 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[4]W1CX Sticky bits indicating various errors on lane 4. See description for LANE_ERROR[0]

8.3.7.63 LANE_ERROR_5 Register (Offset = 0x165) [Reset = 0xXX]

LANE_ERROR_5 is shown in Table 8-134.

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Table 8-134 LANE_ERROR_5 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[5]W1CX Sticky bits indicating various errors on lane 5. See description for LANE_ERROR[0]

8.3.7.64 LANE_ERROR_6 Register (Offset = 0x166) [Reset = 0xXX]

LANE_ERROR_6 is shown in Table 8-135.

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Table 8-135 LANE_ERROR_6 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[6]W1CX Sticky bits indicating various errors on lane 6. See description for LANE_ERROR[0]

8.3.7.65 LANE_ERROR_7 Register (Offset = 0x167) [Reset = 0xXX]

LANE_ERROR_7 is shown in Table 8-136.

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Table 8-136 LANE_ERROR_7 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[7]W1CX Sticky bits indicating various errors on lane 7. See description for LANE_ERROR[0]

8.3.7.66 LANE_ERROR_8 Register (Offset = 0x168) [Reset = 0xXX]

LANE_ERROR_8 is shown in Table 8-137.

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Table 8-137 LANE_ERROR_8 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[8]W1CX Sticky bits indicating various errors on lane 8. See description for LANE_ERROR[0]

8.3.7.67 LANE_ERROR_9 Register (Offset = 0x169) [Reset = 0xXX]

LANE_ERROR_9 is shown in Table 8-138.

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Table 8-138 LANE_ERROR_9 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[9]W1CX Sticky bits indicating various errors on lane 9. See description for LANE_ERROR[0]

8.3.7.68 LANE_ERROR_10 Register (Offset = 0x16A) [Reset = 0xXX]

LANE_ERROR_10 is shown in Table 8-139.

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Table 8-139 LANE_ERROR_10 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[10]W1CX Sticky bits indicating various errors on lane 10. See description for LANE_ERROR[0]

8.3.7.69 LANE_ERROR_11 Register (Offset = 0x16B) [Reset = 0xXX]

LANE_ERROR_11 is shown in Table 8-140.

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Table 8-140 LANE_ERROR_11 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[11]W1CX Sticky bits indicating various errors on lane 11. See description for LANE_ERROR[0]

8.3.7.70 LANE_ERROR_12 Register (Offset = 0x16C) [Reset = 0xXX]

LANE_ERROR_12 is shown in Table 8-141.

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Table 8-141 LANE_ERROR_12 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[12]W1CX Sticky bits indicating various errors on lane 12. See description for LANE_ERROR[0]

8.3.7.71 LANE_ERROR_13 Register (Offset = 0x16D) [Reset = 0xXX]

LANE_ERROR_13 is shown in Table 8-142.

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Table 8-142 LANE_ERROR_13 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[13]W1CX Sticky bits indicating various errors on lane 13. See description for LANE_ERROR[0]

8.3.7.72 LANE_ERROR_14 Register (Offset = 0x16E) [Reset = 0xXX]

LANE_ERROR_14 is shown in Table 8-143.

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Table 8-143 LANE_ERROR_14 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[14]W1CX Sticky bits indicating various errors on lane 14. See description for LANE_ERROR[0]

8.3.7.73 LANE_ERROR_15 Register (Offset = 0x16F) [Reset = 0xXX]

LANE_ERROR_15 is shown in Table 8-144.

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Table 8-144 LANE_ERROR_15 Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERROR[15]W1CX Sticky bits indicating various errors on lane 15. See description for LANE_ERROR[0]

8.3.7.74 FIFO_STATUS_0 Register (Offset = 0x170) [Reset = 0xXX]

FIFO_STATUS_0 is shown in Table 8-145.

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Table 8-145 FIFO_STATUS_0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDRX
5-0PDIFFRX This register returns the difference between the write and read pointers inside the gearbox FIFO for logical lane 0.

8.3.7.75 FIFO_STATUS_1 Register (Offset = 0x171) [Reset = 0xXX]

FIFO_STATUS_1 is shown in Table 8-146.

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Table 8-146 FIFO_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[1]RX See description for FIFO_STATUS[0]

8.3.7.76 FIFO_STATUS_2 Register (Offset = 0x172) [Reset = 0xXX]

FIFO_STATUS_2 is shown in Table 8-147.

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Table 8-147 FIFO_STATUS_2 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[2]RX See description for FIFO_STATUS[0]

8.3.7.77 FIFO_STATUS_3 Register (Offset = 0x173) [Reset = 0xXX]

FIFO_STATUS_3 is shown in Table 8-148.

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Table 8-148 FIFO_STATUS_3 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[3]RX See description for FIFO_STATUS[0]

8.3.7.78 FIFO_STATUS_4 Register (Offset = 0x174) [Reset = 0xXX]

FIFO_STATUS_4 is shown in Table 8-149.

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Table 8-149 FIFO_STATUS_4 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[4]RX See description for FIFO_STATUS[0]

8.3.7.79 FIFO_STATUS_5 Register (Offset = 0x175) [Reset = 0xXX]

FIFO_STATUS_5 is shown in Table 8-150.

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Table 8-150 FIFO_STATUS_5 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[5]RX See description for FIFO_STATUS[0]

8.3.7.80 FIFO_STATUS_6 Register (Offset = 0x176) [Reset = 0xXX]

FIFO_STATUS_6 is shown in Table 8-151.

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Table 8-151 FIFO_STATUS_6 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[6]RX See description for FIFO_STATUS[0]

8.3.7.81 FIFO_STATUS_7 Register (Offset = 0x177) [Reset = 0xXX]

FIFO_STATUS_7 is shown in Table 8-152.

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Table 8-152 FIFO_STATUS_7 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[7]RX See description for FIFO_STATUS[0]

8.3.7.82 FIFO_STATUS_8 Register (Offset = 0x178) [Reset = 0xXX]

FIFO_STATUS_8 is shown in Table 8-153.

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Table 8-153 FIFO_STATUS_8 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[8]RX See description for FIFO_STATUS[0]

8.3.7.83 FIFO_STATUS_9 Register (Offset = 0x179) [Reset = 0xXX]

FIFO_STATUS_9 is shown in Table 8-154.

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Table 8-154 FIFO_STATUS_9 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[9]RX See description for FIFO_STATUS[0]

8.3.7.84 FIFO_STATUS_10 Register (Offset = 0x17A) [Reset = 0xXX]

FIFO_STATUS_10 is shown in Table 8-155.

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Table 8-155 FIFO_STATUS_10 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[10]RX See description for FIFO_STATUS[0]

8.3.7.85 FIFO_STATUS_11 Register (Offset = 0x17B) [Reset = 0xXX]

FIFO_STATUS_11 is shown in Table 8-156.

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Table 8-156 FIFO_STATUS_11 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[11]RX See description for FIFO_STATUS[0]

8.3.7.86 FIFO_STATUS_12 Register (Offset = 0x17C) [Reset = 0xXX]

FIFO_STATUS_12 is shown in Table 8-157.

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Table 8-157 FIFO_STATUS_12 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[12]RX See description for FIFO_STATUS[0]

8.3.7.87 FIFO_STATUS_13 Register (Offset = 0x17D) [Reset = 0xXX]

FIFO_STATUS_13 is shown in Table 8-158.

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Table 8-158 FIFO_STATUS_13 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[13]RX See description for FIFO_STATUS[0]

8.3.7.88 FIFO_STATUS_14 Register (Offset = 0x17E) [Reset = 0xXX]

FIFO_STATUS_14 is shown in Table 8-159.

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Table 8-159 FIFO_STATUS_14 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[14]RX See description for FIFO_STATUS[0]

8.3.7.89 FIFO_STATUS_15 Register (Offset = 0x17F) [Reset = 0xXX]

FIFO_STATUS_15 is shown in Table 8-160.

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Table 8-160 FIFO_STATUS_15 Register Field Descriptions
BitFieldTypeResetDescription
7-0FIFO_STATUS[15]RX See description for FIFO_STATUS[0]

8.3.7.90 JCAP_ARM Register (Offset = 0x18A) [Reset = 0x00]

JCAP_ARM is shown in Table 8-161.

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Table 8-161 JCAP_ARM Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0JCAP_ARMR/W0x0 Transitioning this bit from 0 to 1 will arm the capture debug system to capture on the next JCAP trigger event. Only a single capture will occur each time the system is armed.

8.3.7.91 JCAP_MODE Register (Offset = 0x18B) [Reset = 0x00]

JCAP_MODE is shown in Table 8-162.

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Table 8-162 JCAP_MODE Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0JCAP_MODER/W0x0 Selects the debug capture mode
0x0 = [JESD_JCAP_LINKIN] Capture the input of the link layer (gearbox output). Trigger immediately after JCAP_ARM is set. If JCAP_ARM is set before SYS_EN, trigger when SYS_EN is set and the gearbox has released (gearboxes for different lanes may release at different times).
0x1 = [JESD_JCAP_LINKOUT] Captures the output of the link layer. Trigger on next start of MF/EMB after JCAP_ARM is set. If JCAP_ARM is set before SYS_EN the trigger will occur on the first MF/EMB from the lane. (This allows capturing the ILAS in 8b/10b mode.) Note: Different lanes may trigger on different MF/EMB boundaries (this applies to 64b/66b or 8b/10b if the link is up before JCAP_ARM is set).
0x2 = [JESD_JCAP_TRANS] Captures the output of the transport layer. Trigger immediately after JCAP_ARM is set. This should only be used when LINK_UP=1. JCAP_OFFSET is ignored in this mode.
0x3-0xF = Reserved

8.3.7.92 JCAP_OFFSET Register (Offset = 0x18C) [Reset = 0x0000]

JCAP_OFFSET is shown in Table 8-163.

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Table 8-163 JCAP_OFFSET Register Field Descriptions
BitFieldTypeResetDescription
15-0JCAP_OFFSETR/W0x0 Delay the start of capture until JCAP_OFFSET*8 octets after the JCAP trigger event defined by JCAP_MODE.

8.3.7.93 JCAP_PAGE Register (Offset = 0x18E) [Reset = 0x00]

JCAP_PAGE is shown in Table 8-164.

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Table 8-164 JCAP_PAGE Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0x0
4-0JCAP_PAGER/W0x0 Selects which logical page to access captured data from when reading JCAP or JCAP_STATUS. When JCAP_MODE < 2, only the first 16 pages are valid and correspond to the logical lanes. For JCAP_MODE=2, the first 32 pages are valid and map data as shown in Transport Layer Debug Capture.
You may write JCAP_PAGE as needed to access status and data from all lanes.

8.3.7.94 JCAP_STATUS Register (Offset = 0x18F) [Reset = 0x00]

JCAP_STATUS is shown in Table 8-165.

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Table 8-165 JCAP_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0JCAP_STATUSR/W0x0 When this bit returns a 1, it indicates that the lane specified by JCAP_PAGE has completed its capture, and data is available to be read from JCAP. This bit is reset any time JCAP_ARM=0, SYS_EN=0 , or JESD_RST=1. Before reading JCAP_STATUS, program JCAP_PAGE.
Note: When JCAP_MODE < 2, each of the 16 JCAP_PAGEs will contain a unique JCAP_STATUS. When JCAP_MODE=2, JCAP_STATUS is only defined when JCAP_PAGE=0.

8.3.7.95 JCAP Register (Offset = 0x190) [Reset = 0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]

JCAP is shown in Table 8-166.

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Table 8-166 JCAP Register Field Descriptions
BitFieldTypeResetDescription
127-0JCAPRX When capturing physical or link layer data, address 0x0190 is the first byte captured, and 0x019F is the last byte captured. Within each byte, bit 7 is the first bit captured and bit 0 is the last bit captured. When capturing transport layer data, refer to Transport Layer Debug Capture.
Before reading JCAP, program JCAP_PAGE. Unless JCAP_STATUS=1, the values returned here are undefined.

8.3.7.96 LEC_CTRL Register (Offset = 0x1A0) [Reset = 0x02]

LEC_CTRL is shown in Table 8-167.

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Table 8-167 LEC_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-2LEC_CNT_SELR/W0x0 Select which lane error counters are accessible in LEC_CNT.
  • 0x0 = BER Counters
  • 0x1 = FEC Correctable Error Counters
  • 0x2 = FEC Uncorrectable Error Counters
  • 0x3 = RESERVED
1FEC_EM_ENR/W0x1 When this bit is set, JENC=1, and SHMODE=2, the FEC error counters will count the number of multi-blocks with FEC errors. To clear and restart the counters, program FEC_EM_EN to 0 and then back to 1.
0BER_ENR/W0x0 After setting up the receiver parameters, the user can program JTEST to a PRBS mode, ensure the JESD interface is enabled (see DSP_MODE), set SYS_EN, and then set BER_EN to enable the BER counters (see LEC_CNTn). To clear and restart the counters, program BER_EN to 0 and then back to 1. The BER logic will self-synchronize to the incoming PRBS data after the rising edge of BER_EN.

8.3.7.97 LEC_CNT_0 Register (Offset = 0x1B0) [Reset = 0xXX]

LEC_CNT_0 is shown in Table 8-168.

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Table 8-168 LEC_CNT_0 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[0]RX Returns the number of errors detected on lane 0 by the error counters selected in LEC_CNT_SEL. This value will saturate at 255.
For the BER counters, the bit-error-rate for lane n can be computed as follows:
BER = LEC_CNT[0] / FBIT / TBER
Where TBER is the number of seconds that has elapsed from when BER_EN was set to when LEC_CNT[n] was read. TBER is measured by the host system or clock.
For the FEC counters, the multi-block error rate (MER) for lane n can be computed as follows:
MER = LEC_CNT[0] / (66*32*FBIT) / TMER
Where TMER is the number of seconds that elapsed between when the error counters were started and when LEC_CNT[0] was read. TMER is measured by the host system or clock. The FEC error counters are reset when SYS_EN=0, JESD_RST=1, FEC_EM_EN=0, or JTimer expires (see JTIMER).
Note: The error counters on disabled lanes and lanes enabled by EXTRA_LANE are undefined.
Note: User must wait at least 1us after enabling the counters (using either BER_EN or FEC_EM_EN) before reading this register.

8.3.7.98 LEC_CNT_1 Register (Offset = 0x1B1) [Reset = 0xXX]

LEC_CNT_1 is shown in Table 8-169.

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Table 8-169 LEC_CNT_1 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[1]RX See description for LEC_CNT[0]

8.3.7.99 LEC_CNT_2 Register (Offset = 0x1B2) [Reset = 0xXX]

LEC_CNT_2 is shown in Table 8-170.

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Table 8-170 LEC_CNT_2 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[2]RX See description for LEC_CNT[0]

8.3.7.100 LEC_CNT_3 Register (Offset = 0x1B3) [Reset = 0xXX]

LEC_CNT_3 is shown in Table 8-171.

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Table 8-171 LEC_CNT_3 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[3]RX See description for LEC_CNT[0]

8.3.7.101 LEC_CNT_4 Register (Offset = 0x1B4) [Reset = 0xXX]

LEC_CNT_4 is shown in Table 8-172.

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Table 8-172 LEC_CNT_4 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[4]RX See description for LEC_CNT[0]

8.3.7.102 LEC_CNT_5 Register (Offset = 0x1B5) [Reset = 0xXX]

LEC_CNT_5 is shown in Table 8-173.

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Table 8-173 LEC_CNT_5 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[5]RX See description for LEC_CNT[0]

8.3.7.103 LEC_CNT_6 Register (Offset = 0x1B6) [Reset = 0xXX]

LEC_CNT_6 is shown in Table 8-174.

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Table 8-174 LEC_CNT_6 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[6]RX See description for LEC_CNT[0]

8.3.7.104 LEC_CNT_7 Register (Offset = 0x1B7) [Reset = 0xXX]

LEC_CNT_7 is shown in Table 8-175.

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Table 8-175 LEC_CNT_7 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[7]RX See description for LEC_CNT[0]

8.3.7.105 LEC_CNT_8 Register (Offset = 0x1B8) [Reset = 0xXX]

LEC_CNT_8 is shown in Table 8-176.

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Table 8-176 LEC_CNT_8 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[8]RX See description for LEC_CNT[0]

8.3.7.106 LEC_CNT_9 Register (Offset = 0x1B9) [Reset = 0xXX]

LEC_CNT_9 is shown in Table 8-177.

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Table 8-177 LEC_CNT_9 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[9]RX See description for LEC_CNT[0]

8.3.7.107 LEC_CNT_10 Register (Offset = 0x1BA) [Reset = 0xXX]

LEC_CNT_10 is shown in Table 8-178.

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Table 8-178 LEC_CNT_10 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[10]RX See description for LEC_CNT[0]

8.3.7.108 LEC_CNT_11 Register (Offset = 0x1BB) [Reset = 0xXX]

LEC_CNT_11 is shown in Table 8-179.

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Table 8-179 LEC_CNT_11 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[11]RX See description for LEC_CNT[0]

8.3.7.109 LEC_CNT_12 Register (Offset = 0x1BC) [Reset = 0xXX]

LEC_CNT_12 is shown in Table 8-180.

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Table 8-180 LEC_CNT_12 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[12]RX See description for LEC_CNT[0]

8.3.7.110 LEC_CNT_13 Register (Offset = 0x1BD) [Reset = 0xXX]

LEC_CNT_13 is shown in Table 8-181.

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Table 8-181 LEC_CNT_13 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[13]RX See description for LEC_CNT[0]

8.3.7.111 LEC_CNT_14 Register (Offset = 0x1BE) [Reset = 0xXX]

LEC_CNT_14 is shown in Table 8-182.

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Table 8-182 LEC_CNT_14 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[14]RX See description for LEC_CNT[0]

8.3.7.112 LEC_CNT_15 Register (Offset = 0x1BF) [Reset = 0xXX]

LEC_CNT_15 is shown in Table 8-183.

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Table 8-183 LEC_CNT_15 Register Field Descriptions
BitFieldTypeResetDescription
7-0LEC_CNT[15]RX See description for LEC_CNT[0]